PIC24HJ12GP201-I/P Microchip Technology, PIC24HJ12GP201-I/P Datasheet - Page 127

• Manufacturer Part Number: PIC24HJ12GP201-I/P
• Description: IC PIC MCU FLASH 4KX24 18DIP
• Manufacturer: Microchip Technology
• Series: PIC® 24Hr

Specifications of PIC24HJ12GP201-I/P

• Program Memory Type: FLASH
• Program Memory Size: 12KB (4K x 24)
• Package / Case: 18-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 13
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24HJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6-ch x 10-bit or 6-ch x 12-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164337 - MODULE SOCKET FOR PM3 40DIP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

14.0
The Serial Peripheral Interface (SPI) module is a
synchronous serial interface useful for communicating
with other peripheral or microcontroller devices. These
peripheral devices can be serial EEPROMs, shift
registers, display drivers, analog-to-digital (A/D)
converters, etc. The SPI module is compatible with
SPI and SIOP from Motorola
Each SPI module consists of a 16-bit shift register,
SPIxSR (where x = 1 or 2), used for shifting data in and
out, and a buffer register, SPIxBUF. A control register,
SPIxCON, configures the module. Additionally, a status
register, SPIxSTAT, indicates status conditions.
The serial interface consists of 4 pins:
• SDIx (serial data input)
• SDOx (serial data output)
• SCKx (shift clock input or output)
• SSx (active low slave select).
In Master mode operation, SCK is a clock output. In
Slave mode, it is a clock input.
14.1
A series of 8 or 16 clock pulses shift out bits from the
SPIxSR to SDOx pin and simultaneously shift in data
from the SDIx pin. An interrupt is generated when the
transfer is complete and the corresponding interrupt flag
bit (SPI1IF) is set. This interrupt can be disabled through
an interrupt enable bit (SPI1IE).
14.2
The receive operation is double-buffered. When a
complete byte is received, it is transferred from
SPIxSR to SPIxBUF.
If the receive buffer is full when new data is being
transferred from SPIxSR to SPIxBUF, the module sets
the SPIROV bit, indicating an overflow condition. The
transfer of the data from SPIxSR to SPIxBUF is not
completed, and the new data is lost. The module will
not respond to SCL transitions while SPIROV is ‘1’,
effectively disabling the module until SPIxBUF is read
by user software.
© 2007 Microchip Technology Inc.
Note:
SERIAL PERIPHERAL
INTERFACE (SPI)
Interrupts
Receive Operations
This data sheet summarizes the features
of the PIC24HJ12GP201/202 devices. It is
not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to the
“PIC24H
Please see the Microchip web site
(www.microchip.com)
PIC24H
chapters.
Family
Family
®
.
Reference
Reference
for
the
Manual”.
Manual
latest
Preliminary
PIC24HJ12GP201/202
14.3
Transmit writes are also double-buffered. The user
application writes to SPIxBUF. When the Master or
Slave transfer is completed, the contents of the shift
register (SPIxSR) are moved to the receive buffer. If any
transmit data has been written to the buffer register, the
contents of the transmit buffer are moved to SPIxSR.
The received data is thus placed in SPIxBUF and the
transmit data in SPIxSR is ready for the next transfer.
14.4
To set up the SPI module for the Master mode of
operation:
1.
2.
3.
4.
5.
To set up the SPI module for the Slave mode of operation:
1.
2.
3.
4.
5.
6.
7.
The SPI module generates an interrupt indicating
completion of a byte or word transfer, as well as a
separate interrupt for all SPI error conditions.
Note:
If using interrupts:
a)
b)
c)
Write the desired settings to the SPIxCON
register with MSTEN (SPIxCON1<5>) = 1.
Clear the SPIROV bit (SPIxSTAT<6>).
Enable SPI operation by setting the SPIEN bit
(SPIxSTAT<15>).
Write the data to be transmitted to the SPIxBUF
register. Transmission (and reception) will start as
soon as data is written to the SPIxBUF register.
Clear the SPIxBUF register.
If using interrupts:
a)
b)
c)
Write the desired settings to the SPIxCON1 and
SPIxCON2
(SPIxCON1<5>) = 0.
Clear the SMP bit.
If the CKE bit is set, then set the SSEN bit
(SPIxCON1<7>) to enable the SSx pin.
Clear the SPIROV bit (SPIxSTAT<6>).
Enable SPI operation by setting the SPIEN bit
(SPIxSTAT<15>).
Transmit Operations
SPI Setup
Clear the SPIxIF bit in the respective IFSn
register.
Set the SPIxIE bit in the respective IECn
register.
Write the SPIxIP bits in the respective IPCn
register to set the interrupt priority.
Clear the SPIxIF bit in the respective IFSn
register.
Set the SPIxIE bit in the respective IECn
register.
Write the SPIxIP bits in the respective IPCn
register to set the interrupt priority.
Both the transmit buffer (SPIxTXB) and
the receive buffer (SPIxRXB) are mapped
to the same register address, SPIxBUF.
Do not perform read-modify-write opera-
tions (such as bit-oriented instructions) on
the SPIxBUF register.
registers
with
DS70282B-page 125
MSTEN