PIC24HJ12GP201-I/P Microchip Technology, PIC24HJ12GP201-I/P Datasheet - Page 40

• Manufacturer Part Number: PIC24HJ12GP201-I/P
• Description: IC PIC MCU FLASH 4KX24 18DIP
• Manufacturer: Microchip Technology
• Series: PIC® 24Hr

Specifications of PIC24HJ12GP201-I/P

• Program Memory Type: FLASH
• Program Memory Size: 12KB (4K x 24)
• Package / Case: 18-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 13
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24HJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6-ch x 10-bit or 6-ch x 12-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164337 - MODULE SOCKET FOR PM3 40DIP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC24HJ12GP201/202
4.2
The PIC24HJ12GP201/202 Flash program memory
array is organized into rows of 64 instructions or 192
bytes. RTSP allows the user application to erase a
page of memory, which consists of eight rows (512
instructions) at a time, and to program one row or one
word at a time. The 8-row erase pages and single row
write rows are edge-aligned from the beginning of
program memory, on boundaries of 1536 bytes and
192 bytes, respectively.
The program memory implements holding buffers that
can contain 64 instructions of programming data. Prior
to the actual programming operation, the write data
must be loaded into the buffers sequentially. The
instruction words loaded must always be from a group
of 64 boundary.
The basic sequence for RTSP programming is to set up
a Table Pointer, then do a series of TBLWT instructions
to load the buffers. Programming is performed by
setting the control bits in the NVMCON register. A total
of 64 TBLWTL and TBLWTH instructions are required
to load the instructions.
All of the table write operations are single-word writes
(two instruction cycles) because only the buffers are
written.
programming each row.
DS70282B-page 38
RTSP Operation
A
programming
cycle
is
required
Preliminary
for
4.3
Two SFRs are used to read and write the program
Flash memory:
• NVMCON: Flash Memory Control Register
• NVMKEY: NonVolatile Memory Key Register
The NVMCON register (Register 4-1) controls which
blocks are to be erased, which memory type is to be
programmed and the start of the programming cycle.
NVMKEY (Register 4-2) is a write-only register that is
used for write protection. To start a programming or
erase
consecutively write 55h and AAh to the NVMKEY
register.
Operations” for further details.
4.4
A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode. A programming operation is nominally 4 ms in
duration and the processor stalls (waits) until the
operation
(NVMCON<15>) starts the operation, and the WR bit is
automatically cleared when the operation is finished.
sequence,
Control Registers
Programming Operations
Refer
is
finished.
to
the
© 2007 Microchip Technology Inc.
Section 4.4
user
Setting
application
“Programming
the
WR
must
bit