ATMEGA8515L-8PU Atmel, ATMEGA8515L-8PU Datasheet - Page 29

• Manufacturer Part Number: ATMEGA8515L-8PU
• Description: IC AVR MCU 8K 8MHZ 3V 40DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8515L-8PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: ATMEGA8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI, USART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• Cpu Family: ATmega
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 8MHz
• Total Internal Ram Size: 512Byte
• # I/os (max): 35
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 40
• Package Type: PDIP W
• Controller Family/series: AVR MEGA
• No. Of I/o's: 35
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 8MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

2512F–AVR–12/03
SRAM address space is configured as one sector, the wait states are configured by the
SRW11 and SRW10 bits.
Table 2. Sector Limits with Different Settings of SRL2..0
• Bit 1 and Bit 6 MCUCR – SRW11, SRW10: Wait State Select Bits for Upper
The SRW11 and SRW10 bits control the number of wait states for the upper sector of
the External Memory address space, see Table 3.
• Bit 3..2 – SRW01, SRW00: Wait State Select Bits for Lower Sector
The SRW01 and SRW00 bits control the number of wait states for the lower sector of
the External Memory address space, see Table 3.
Table 3. Wait States
Note:
SRWn1
Sector
SRL2
0
0
1
1
0
0
0
0
1
1
1
1
1. n = 0 or 1 (lower/upper sector).
SRWn0
For further details of the timing and wait states of the External Memory Interface, see
Figure 13 to Figure 16 how the setting of the SRW bits affects the timing.
0
1
0
1
SRL1
0
0
1
1
0
0
1
1
(1)
Wait States
No wait states.
Wait one cycle during read/write strobe.
Wait two cycles during read/write strobe.
Wait two cycles during read/write and wait one cycle before driving out
new address.
SRL0
0
1
0
1
0
1
0
1
Sector Limits
Lower sector = N/A
Upper sector = 0x0260 - 0xFFFF
Lower sector = 0x0260 - 0x1FFF
Upper sector = 0x2000 - 0xFFFF
Lower sector = 0x0260 - 0x3FFF
Upper sector = 0x4000 - 0xFFFF
Lower sector = 0x0260 - 0x5FFF
Upper sector = 0x6000 - 0xFFFF
Lower sector = 0x0260 - 0x7FFF
Upper sector = 0x8000 - 0xFFFF
Lower sector = 0x0260 - 0x9FFF
Upper sector = 0xA000 - 0xFFFF
Lower sector = 0x0260 - 0xBFFF
Upper sector = 0xC000 - 0xFFFF
Lower sector = 0x0260 - 0xDFFF
Upper sector = 0xE000 - 0xFFFF
ATmega8515(L)
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