ATMEGA8515L-8PU Atmel, ATMEGA8515L-8PU Datasheet - Page 92

IC AVR MCU 8K 8MHZ 3V 40DIP

ATMEGA8515L-8PU

Manufacturer Part Number
ATMEGA8515L-8PU
Description
IC AVR MCU 8K 8MHZ 3V 40DIP
Manufacturer
Atmel
Series
AVR® ATmegar

Specifications of ATMEGA8515L-8PU

Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
EBI/EMI, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
ATMEGA8x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SPI, USART
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
35
Number Of Timers
2
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Minimum Operating Temperature
- 40 C
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
8MHz
Total Internal Ram Size
512Byte
# I/os (max)
35
Number Of Timers - General Purpose
2
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Through Hole
Pin Count
40
Package Type
PDIP W
Controller Family/series
AVR MEGA
No. Of I/o's
35
Eeprom Memory Size
512Byte
Ram Memory Size
512Byte
Cpu Speed
8MHz
Rohs Compliant
Yes
For Use With
ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Timer/Counter Register –
TCNT0
Output Compare Register –
OCR0
Timer/Counter Interrupt Mask
Register – TIMSK
Timer/Counter Interrupt Flag
Register – TIFR
92
ATmega8515(L)
Table 48. Clock Select Bit Description
If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will
clock the counter even if the pin is configured as an output. This feature allows software
control of the counting.
The Timer/Counter Register gives direct access, both for read and write operations, to
the Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes)
the Compare Match on the following timer clock. Modifying the counter (TCNT0) while
the counter is running, introduces a risk of missing a Compare Match between TCNT0
and the OCR0 Register.
The Output Compare Register contains an 8-bit value that is continuously compared
with the counter value (TCNT0). A match can be used to generate an output compare
interrupt, or to generate a waveform output on the OC0 pin.
• Bit 1 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is written to one, and the I-bit in the Status Register is set (one), the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if
an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the
Timer/Counter Interrupt Flag Register – TIFR.
• Bit 0 – OCIE0: Timer/Counter0 Output Compare Match Interrupt Enable
When the OCIE0 bit is written to one, and the I-bit in the Status Register is set (one), the
Timer/Counter0 Compare Match interrupt is enabled. The corresponding interrupt is
executed if a Compare Match in Timer/Counter0 occurs, i.e., when the OCF0 bit is set in
the Timer/Counter Interrupt Flag Register – TIFR.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
CS02
0
1
1
1
1
CS01
1
0
0
1
1
TOIE1
R/W
R/W
R/W
7
0
7
0
7
0
7
CS00
OCIE1A
1
0
1
0
1
R/W
R/W
R/W
6
0
6
0
6
0
6
Description
clk
clk
clk
External clock source on T0 pin. Clock on falling edge.
External clock source on T0 pin. Clock on rising edge.
OCIE1B
R/W
R/W
R/W
I/O
I/O
I/O
5
0
5
0
5
5
0
/64 (From prescaler)
/256 (From prescaler)
/1024 (From prescaler)
R/W
R/W
R/W
4
0
4
0
4
TCNT0[7:0]
4
0
OCR0[7:0]
TICIE1
R/W
R/W
R/W
3
0
3
0
3
3
0
R/W
R/W
R/W
2
0
2
0
2
2
0
TOIE0
R/W
R/W
R/W
1
0
1
0
1
1
0
OCIE0
R/W
R/W
R/W
0
0
0
0
0
0
0
2512F–AVR–12/03
TCNT0
OCR0
TIMSK

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