PIC16F87-I/SS Microchip Technology, PIC16F87-I/SS Datasheet - Page 145

• Manufacturer Part Number: PIC16F87-I/SS
• Description: IC MCU FLASH 4KX14 EEPROM 20SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F87-I/SS

• Program Memory Type: FLASH
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 20-SSOP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Eeprom Size: 256 x 8
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 368 B
• Interface Type: SSP/USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT20SS-1 - SOCKET TRANSITION 18DIP 20SSOPAC164307 - MODULE SKT FOR PM3 28SSOP
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

15.12.3
Two-Speed Start-up mode minimizes the latency
between oscillator start-up and code execution that
may be selected with the IESO (Internal/External
Switch Over) bit in Configuration Word 2. This mode is
achieved by initially using the INTRC for code
execution until the primary oscillator is stable.
If this mode is enabled, and any of the following condi-
tions exist, the system will begin execution with the
INTRC oscillator. This results in almost immediate
code execution with a minimum of delay.
• POR and after the Power-up Timer has expired (if
• or following a wake-up from SLEEP,
• or a RESET when running from T1OSC or INTRC
If the primary oscillator is configured to be anything
other than XT, LP, or HS, then Two-Speed Start-up
mode is disabled, because the primary oscillator will
not require any time to become stable after POR, or an
exit from SLEEP.
If the IRCF bits of the OSCCON register are configured
to a non-zero value prior to entering SLEEP mode, the
system clock frequency will come from the output of
the INTOSC. The IOFS bit in the OSCCON register will
be clear until the INTOSC is stable. This will allow the
user to determine when the internal oscillator can be
used for time critical applications.
FIGURE 15-9:
 2003 Microchip Technology Inc.
System Clock
PWRTEN = 0),
(after a RESET, SCS<1:0> are always set to ‘00’).
Note:
Program
Counter
SLEEP
INTRC
OSC1
OSC2
OSTS
TWO-SPEED CLOCK START-UP
MODE
Following any RESET, the IRCF bits are
zeroed and the frequency selection is
forced to 31.25 kHz. The user can modify
the IRCF bits to select a higher internal
oscillator frequency.
PC
TWO-SPEED START-UP MODE
CPU Start-up
Q1
T
OST
Q4
Q1 Q2 Q3 Q4 Q1 Q2
0000h
Preliminary
Checking the state of the OSTS bit will confirm
whether the primary clock configuration is engaged. If
not, the OSTS bit will remain clear.
When the device is auto-configured in INTRC mode fol-
lowing a POR or wake-up from SLEEP, the rules for
entering other oscillator modes still apply, meaning the
SCS<1:0> bits in OSCCON can be modified before the
OST time-out has occurred. This would allow the appli-
cation to wake-up from SLEEP, perform a few instruc-
tions using the INTRC as the clock source and go back
to SLEEP without waiting for the primary oscillator to
become stable.
15.12.3.1
1.
2.
3.
4.
5.
6.
7.
8.
The software may read the OSTS bit to determine
when the switch over takes place so that any software
timing edges can be adjusted.
0001h
Note:
Q3 Q4 Q1 Q2
Wake-up from SLEEP, RESET, or POR.
OSCON bits configured to run from INTRC
(31.25 kHz).
Instructions
(31.25 kHz).
OST enabled to count 1024 clock cycles.
OST timed out, wait for falling edge of INTRC.
OSTS is set.
System clock held low for eight falling edges of
new clock (LP, XT, or HS).
System clock is switched to primary source (LP,
XT, or HS).
Executing a SLEEP instruction will abort
the oscillator start-up time and will cause
the OSTS bit to remain clear.
Two-Speed Start-up Mode
Sequence
0003h
begin
Q3 Q4
PIC16F87/88
Q1 Q2 Q3 Q4
execution
0004h
DS30487B-page 143
by
0005h
INTRC