PIC18F4321-I/PT Microchip Technology, PIC18F4321-I/PT Datasheet - Page 274

IC PIC MCU FLASH 4KX16 44TQFP

PIC18F4321-I/PT

Manufacturer Part Number
PIC18F4321-I/PT
Description
IC PIC MCU FLASH 4KX16 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F4321-I/PT

Program Memory Type
FLASH
Program Memory Size
8KB (4K x 16)
Package / Case
44-TQFP, 44-VQFP
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
EUSART/I2C/MSSP/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
36
Number Of Timers
4
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
13-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPAC164305 - MODULE SKT FOR PM3 44TQFP444-1001 - DEMO BOARD FOR PICMICRO MCUAC164020 - MODULE SKT PROMATEII 44TQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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PIC18F4321-I/PT
0
PIC18F2221/2321/4221/4321 FAMILY
24.5
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PIC
The user program memory is divided into three blocks.
One of these is a boot block of variable size. The
remainder of the memory is divided into two blocks on
binary boundaries.
FIGURE 24-5:
DS39689F-page 274
®
devices.
Boot Block
2K words
1K word
1K word
11/10
Block 0
Block 1
Program Verification and
Code Protection
Unimplemented
(PIC18FX321)
Reads all ‘0’s
1.5K words
Boot Block
512 words
2K words
8 Kbytes
CODE-PROTECTED PROGRAM MEMORY FOR PIC18F2221/2321/4221/4321
FAMILY DEVICES
Block 0
Block 1
01
MEMORY SIZE/DEVICE
1.75K words
BBSIZ<1:0>
Boot Block
256 words
2K words
Block 0
Block 1
00
11/10/01
0.5K words
Boot Block
512 words
1K word
Block 0
Block 1
Unimplemented
(PIC18FX221)
Reads all ‘0’s
4 Kbytes
Each of the three blocks has three code protection bits
associated with them. They are:
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 24-5 shows the program memory organization
for 4 and 8-Kbyte devices and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table 24-3.
0.75K words
Boot Block
256 words
1K word
Block 0
Block 1
00
000000h
0001FFh
000200h
0003FFh
000400h
0007FFh
000800h
000FFFh
001000h
001FFFh
002000h
1FFFFFh
Address
Range
© 2009 Microchip Technology Inc.
(Unimplemented Memory
Block Code Protection
CPB, WRTB, EBTRB
CP0, WRT0, EBTR0
CP1, WRT1, EBTR1
Controlled By:
Space)

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