PIC16LF872-I/SP Microchip Technology, PIC16LF872-I/SP Datasheet - Page 164

• Manufacturer Part Number: PIC16LF872-I/SP
• Description: IC MCU FLASH 2KX14 EE A/D 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16LF872-I/SP

• Core Size: 8-Bit
• Program Memory Size: 3.5KB (2K x 14)
• Oscillator Type: External
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Controller Family/series: PIC16LF
• No. Of I/o's: 22
• Eeprom Memory Size: 64Byte
• Ram Memory Size: 128Byte
• Cpu Speed: 20MHz
• No.: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F872
Timing Parameter Symbology ......................................... 126
TMR0 Register .............................................................. 9
TMR1CS bit ....................................................................... 39
TMR1H Register .................................................................. 9
TMR1L Register ................................................................... 9
TMR1ON bit ....................................................................... 39
TMR2 Register ..................................................................... 9
TOUTPS3:TOUTPS0 bits .................................................. 43
TRISA Register .................................................................. 10
TRISB Register .................................................................. 10
TRISC Register .................................................................. 10
DS30221C-page 162
Bus Collision During START Condition
Bus Collision During START Condition
Capture/Compare/PWM .......................................... 131
CLKOUT and I/O ..................................................... 128
External Clock .......................................................... 127
First START Bit Timing .............................................. 65
I
I
I
I
I
Master Mode Transmit Clock Arbitration ................... 72
Power-up Timer ....................................................... 129
Repeat START Condition .......................................... 66
RESET ..................................................................... 129
Slave Mode General Call Address Sequence
Slow Rise Time (MCLR Tied to V
SPI Master Mode ....................................................... 56
SPI Master Mode (CKE = 0, SMP = 0) .................... 132
SPI Master Mode (CKE = 1, SMP = 1) .................... 132
SPI Slave Mode (CKE = 0) ............................... 57
SPI Slave Mode (CKE = 1) ............................... 57
Start-up Timer .......................................................... 129
STOP Condition Receive or Transmit Mode .............. 72
Time-out Sequence on Power-up .............................. 96
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Timer0 ...................................................................... 130
Timer1 ...................................................................... 130
Wake-up from SLEEP via Interrupt .......................... 101
Watchdog Timer ...................................................... 129
2
2
2
2
2
C Bus Data ............................................................ 135
C Bus START/STOP Bits ...................................... 134
C Master Mode Transmission ................................. 68
C Mode (7-bit Reception) ................................. 60
C Mode (7-bit Transmission) ................................... 61
Case 1 ............................................................... 95
Case 2 ............................................................... 96
(SCL = 0) ................................................... 75
(SDA Only) ................................................ 74
(7 or 10-bit Mode) ...................................... 61
Via RC Network) ........................................ 96
(MCLR Not Tied to V
(MCLR Tied to V
DD
Via RC Network) ........ 95
DD
DD
)
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,
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133
133
70
11
U
UA Bit
W
Wake-up from SLEEP ...............................................87
Wake-Up Using Interrupts ............................................... 100
Watchdog Timer (WDT) ..............................................87
WCOL ................................................................................ 65
WCOL Bit .......................................................................... 53
WCOL Status Flag ........................................ 65
Write Collision Detect Bit (WCOL) ..................................... 53
Write Verify
WWW, On-Line Support ...................................................... 2
Update Address Bit (UA) ........................................... 52
Interrupts ................................................................... 93
MCLR Reset .............................................................. 93
WDT Reset ................................................................ 93
Enable (WDTE Bit) .................................................... 99
Postscaler. See Postscaler, WDT
Programming Considerations .................................... 99
RC Oscillator ............................................................. 99
Time-out Period ......................................................... 99
WDT Reset, Normal Operation ...........................91
WDT Reset, SLEEP ............................................91
WDT Reset, Wake-up ............................................... 93
Data EEPROM and FLASH Program Memory .......... 27
© 2006 Microchip Technology Inc.
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