PIC18F86J90-I/PT Microchip Technology, PIC18F86J90-I/PT Datasheet - Page 320

• Manufacturer Part Number: PIC18F86J90-I/PT
• Description: IC PIC MCU FLASH 64KB 80-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F86J90-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 64KB (32K x 16)
• Package / Case: 80-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 67
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3923 B
• Interface Type: AUSART, EUSART, I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 67
• Number Of Timers: 4
• Operating Supply Voltage: 2.65 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164328 - MODULE SKT FOR 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F87J90 FAMILY
24.6
A unique feature on board the CTMU module is its ability
to generate system clock independent output pulses
based on an external capacitor value. This is accom-
plished using the internal comparator voltage reference
module, Comparator 2 input pin and an external capaci-
tor. The pulse is output onto the CTPLS pin. To enable
this mode, set the TGEN bit.
See Figure 24-4 for an example circuit. C
chosen by the user to determine the output pulse width
on CTPLS. The pulse width is calculated by
T = (C
source measurement step (Section 24.3.1 “Current
Source Calibration”) and V is the internal reference
voltage (CV
FIGURE 24-4:
24.7
24.7.1
When the device enters any Sleep mode, the CTMU
module current source is always disabled. If the CTMU
is performing an operation that depends on the current
source when Sleep mode is invoked, the operation may
not
measurements may return erroneous values.
24.7.2
The behavior of the CTMU in Idle mode is determined
by the CTMUSIDL bit (CTMUCONH<5>). If CTMUSIDL
is cleared, the module will continue to operate in Idle
mode. If CTMUSIDL is set, the module’s current source
is disabled when the device enters Idle mode. If the
module is performing an operation when Idle mode is
invoked, in this case, the results will be similar to those
with Sleep mode.
DS39933D-page 320
terminate
PULSE
Creating a Delay with the CTMU
Module
Operation During Sleep/Idle Modes
REF
/I)*V, where I is known from the current
SLEEP MODE AND DEEP SLEEP
MODES
IDLE MODE
).
correctly.
TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR PULSE
DELAY GENERATION
CTEDG1
C
C2INB
DELAY
Capacitance
and
PULSE
EDG1
time
CV
is
Current Source
REF
PIC18F87J90
Comparator
CTMU
C2
An example use of this feature is for interfacing with
variable capacitive-based sensors, such as a humidity
sensor. As the humidity varies, the pulse-width output
on CTPLS will vary. The CTPLS output pin can be
connected to an input capture pin and the varying pulse
width is measured to determine the humidity in the
application.
Follow these steps to use this feature:
1.
2.
3.
4.
5.
24.8
Upon Reset, all registers of the CTMU are cleared. This
leaves the CTMU module disabled, its current source is
turned off and all configuration options return to their
default settings. The module needs to be re-initialized
following any Reset.
If the CTMU is in the process of taking a measurement
at the time of Reset, the measurement will be lost. A
partial charge may exist on the circuit that was being
measured and should be properly discharged before
the CTMU makes subsequent attempts to make a
measurement. The circuit is discharged by setting and
then clearing the IDISSEN bit (CTMUCONH<1>) while
the A/D Converter is connected to the appropriate
channel.
Initialize Comparator 2.
Initialize the comparator voltage reference.
Initialize the CTMU and enable time delay
generation by setting the TGEN bit.
Set EDG1STAT.
When C
reference trip point, an output pulse is generated
on CTPLS.
Effects of a Reset on CTMU
PULSE
charges to the value of the voltage
CTPLS
 2010 Microchip Technology Inc.