PIC18LF6310-I/PT Microchip Technology, PIC18LF6310-I/PT Datasheet - Page 161

• Manufacturer Part Number: PIC18LF6310-I/PT
• Description: IC PIC MCU FLASH 4KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF6310-I/PT

• Core Size: 8-Bit
• Program Memory Size: 8KB (4K x 16)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 54
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• No. Of Pwm: RoHS Compliant
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.0
PIC18F6310/6410/8310/8410 devices have three CCP
(Capture/Compare/PWM) modules, labelled CCP1,
CCP2 and CCP3. All modules implement standard
Capture, Compare and Pulse-Width Modulation (PWM)
modes.
REGISTER 15-1:
© 2007 Microchip Technology Inc.
CAPTURE/COMPARE/PWM
(CCP) MODULES
bit 7-6
bit 5-4
bit 3-0
CCPxCON: CCP1/CCP2/CCP3 CONTROL REGISTER
bit 7
Unimplemented: Read as ‘0’
DCxB1:DCxB0: PWM Duty Cycle bit 1 and bit 0 for CCP Module x
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two Least Significant bits (bit 1 and bit 0) of the 10-bit PWM Duty Cycle
register. The eight Most Significant bits (DCx9:DCx2) of the PWM Duty Cycle are found in
CCPRxL.
CCPxM3:CCPxM0: CCP Module x Mode Select bits
0000 = Capture/Compare/PWM disabled (resets CCPx module)
0001 = Reserved
0010 = Compare mode, toggle output on match (CCPxIF bit is set)
0011 = Reserved
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode: initialize CCPx pin low; on compare match, force CCPx pin high
1001 = Compare mode: initialize CCPx pin high; on compare match, force CCPx pin low
1010 = Compare mode: generate software interrupt on compare match (CCPxIF bit is set,
1011 = Compare mode: trigger special event, reset timer, start A/D conversion on
11xx = PWM mode
Legend:
R = Readable bit
-n = Value at POR
Note 1: The Special Event Trigger on CCP1 will reset the timer but not start an A/D
U-0
—
2: For CCP3, the Special Event Trigger is not available. This mode functions the same
(CCPxIF bit is set)
(CCPxIF bit is set)
CCPx pin reflects I/O state)
CCPx match (CCPxIF bit is set)
conversion on a CCP1 match.
as Compare Generate Interrupt mode (CCP3M3:CCP3M0 = 1010).
U-0
—
PIC18F6310/6410/8310/8410
DCxB1
R/W-0
Preliminary
W = Writable bit
‘1’ = Bit is set
DCxB0
R/W-0
Each CCP module contains a 16-bit register which can
operate as a 16-bit Capture register, a 16-bit Compare
register or a PWM Master/Slave Duty Cycle register.
For the sake of clarity, all CCP module operation in the
following sections is described with respect to CCP2,
but are equally applicable to CCP1 and CCP3.
(1,2)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
CCPxM3
R/W-0
CCPxM2 CCPxM1 CCPxM0
R/W-0
x = Bit is unknown
R/W-0
DS39635B-page 159
R/W-0
bit 0