PIC18LF6310-I/PT Microchip Technology, PIC18LF6310-I/PT Datasheet - Page 44

• Manufacturer Part Number: PIC18LF6310-I/PT
• Description: IC PIC MCU FLASH 4KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF6310-I/PT

• Core Size: 8-Bit
• Program Memory Size: 8KB (4K x 16)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 54
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• No. Of Pwm: RoHS Compliant
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F6310/6410/8310/8410
3.2.3
In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator block using the
INTOSC multiplexer and the primary clock is shut
down. When using the INTRC source, this mode
provides the best power conservation of all the Run
modes, while still executing code. It works well for user
applications which are not highly timing sensitive, or do
not require high-speed clocks at all times.
If the primary clock source is the internal oscillator block
(either INTRC or INTOSC), there are no distinguishable
differences between PRI_RUN and RC_RUN modes dur-
ing execution. However, a clock switch delay will occur
during entry to and exit from RC_RUN mode. Therefore,
if the primary clock source is the internal oscillator block,
the use of RC_RUN mode is not recommended.
This mode is entered by setting the SCS1 bit to ‘1’.
Although it is ignored, it is recommended that the SCS0
bit also be cleared; this is to maintain software
compatibility with future devices. When the clock
source is switched to the INTOSC multiplexer (see
Figure 3-3), the primary oscillator is shut down and the
OSTS bit is cleared.The IRCF bits may be modified at
any time to immediately change the clock speed.
FIGURE 3-3:
FIGURE 3-4:
DS39635B-page 42
Note:
Peripheral
Program
Counter
INTRC
OSC1
Note 1: T
Clock
Clock
RC_RUN MODE
Caution should be used when modifying a
single IRCF bit. If V
possible to select a higher clock speed
than is supported by the low V
Improper device operation may result if
the V
CPU
CPU Clock
Multiplexer
PLL Clock
Peripheral
Program
INTOSC
Counter
Output
OSC1
Clock
DD
Q1
/F
OST
SCS1:SCS0 bits Changed
OSC
Q2
TRANSITION TIMING TO RC_RUN MODE
TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE
= 1024 T
PC
Q3
specifications are violated.
Q4
OSC
DD
Q1
; T
is less than 3V, it is
PLL
Q1
1
T
= 2 ms (approx). These intervals are not shown to scale.
OST (1)
PC
2
Q2
Clock Transition
3
T
OSTS bit Set
Q3
PLL
DD
Preliminary
(1)
.
PC + 2
n-1
Q4
If the IRCF bits and the INTSRC bit are all clear, the
INTOSC output is not enabled and the IOFS bit will
remain clear; there will be no indication of the current
clock source. The INTRC source is providing the
device clocks.
If the IRCF bits are changed from all clear (thus,
enabling the INTOSC output), or if INTSRC is set, the
IOFS bit becomes set after the INTOSC output
becomes stable. Clocks to the device continue while
the INTOSC source stabilizes after an interval of
T
If the IRCF bits were previously at a non-zero value, or
if INTSRC was set before setting SCS1 and the
INTOSC source was already stable, the IOFS bit will
remain set.
On transitions from RC_RUN mode to PRI_RUN, the
device continues to be clocked from the INTOSC
multiplexer while the primary clock is started. When the
primary clock becomes ready, a clock switch to the
primary clock occurs (see Figure 3-4). When the clock
switch is complete, the IOFS bit is cleared, the OSTS
bit is set and the primary clock is providing the device
clock. The IDLEN and SCS bits are not affected by the
switch. The INTRC source will continue to run if either
the WDT or the Fail-Safe Clock Monitor is enabled.
n
Q1
1
IOBST
Transition
2
Clock
.
n-1 n
Q2
PC + 2
Q3
Q2
Q4
© 2007 Microchip Technology Inc.
Q3 Q4
Q1
Q1
PC + 4
Q2
PC + 4
Q2
Q3
Q3