PIC18LF6310-I/PT Microchip Technology, PIC18LF6310-I/PT Datasheet - Page 215

• Manufacturer Part Number: PIC18LF6310-I/PT
• Description: IC PIC MCU FLASH 4KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF6310-I/PT

• Core Size: 8-Bit
• Program Memory Size: 8KB (4K x 16)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 54
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• No. Of Pwm: RoHS Compliant
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.1
The BRG is a dedicated, 8-bit or 16-bit generator that
supports both the Asynchronous and Synchronous
modes of the EUSART. By default, the BRG operates
in 8-bit mode; setting the BRG16 bit (BAUDCON1<3>)
selects 16-bit mode.
The SPBRGH1:SPBRG1 register pair controls the
period of a free running timer. In Asynchronous mode,
bits BRGH (TXSTA1<2>) and BRG16 (BAUDCON1<3>)
also control the baud rate. In Synchronous mode, BRGH
is ignored. Table 17-1 shows the formula for computa-
tion of the baud rate for different EUSART modes that
only apply in Master mode (internally generated clock).
Given the desired baud rate and F
integer value for the SPBRGH1:SPBRG1 registers can
be calculated using the formulas in Table 17-1. From
this, the error in baud rate can be determined. An
example calculation is shown in Example 17-1. Typical
baud
Asynchronous modes are shown in Table 17-2. It may
TABLE 17-1:
EXAMPLE 17-1:
TABLE 17-2:
© 2007 Microchip Technology Inc.
Legend: x = Don’t care, n = Value of SPBRGH1:SPBRG1 register pair
TXSTA1
RCSTA1
BAUDCON1
SPBRGH1
SPBRG1
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.
For a device with F
Desired Baud Rate
Solving for SPBRGH1:SPBRG1:
Calculated Baud Rate = 16000000/(64 (25 + 1))
Error
SYNC
Name
0
0
0
0
1
1
rates
EUSART Baud Rate Generator
(BRG)
Configuration Bits
and
EUSART1 Baud Rate Generator Register High Byte
EUSART1 Baud Rate Generator Register Low Byte
ABDOVF
CSRC
SPEN
Bit 7
BAUD RATE FORMULAS
BRG16
REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR
OSC
X = ((F
error
0
0
1
1
0
1
CALCULATING BAUD RATE ERROR
= F
= ((16000000/9600)/64) – 1
= [25.042] = 25
= 9615
= (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate
= (9615 – 9600)/9600 = 0.16%
of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG:
RCIDL
values
OSC
Bit 6
RX9
TX9
OSC
/(64 ([SPBRGH1:SPBRG1] + 1))
BRGH
/Desired Baud Rate)/64) – 1
0
1
0
1
x
x
for
OSC
TXEN
SREN
Bit 5
—
, the nearest
the
PIC18F6310/6410/8310/8410
various
CREN
SYNC
SCKP
Bit 4
Preliminary
BRG/EUSART Mode
16-bit/Asynchronous
16-bit/Asynchronous
8-bit/Asynchronous
8-bit/Asynchronous
16-bit/Synchronous
8-bit/Synchronous
SENDB
ADDEN
BRG16
Bit 3
be advantageous to use the high baud rate (BRGH = 1)
or the 16-bit BRG to reduce the baud rate error, or
achieve a slow baud rate for a fast oscillator frequency.
Writing a new value to the SPBRGH1:SPBRG1
registers causes the BRG timer to be reset (or cleared).
This ensures the BRG does not wait for a timer
overflow before outputting the new baud rate.
17.1.1
The device clock is used to generate the desired baud
rate. When one of the power-managed modes is
entered, the new clock source may be operating at a
different frequency. This may require an adjustment to
the value in the SPBRG1 register pair.
17.1.2
The data on the RX1 pin is sampled three times by a
majority detect circuit to determine if a high or a low
level is present at the RX1 pin.
BRGH
FERR
Bit 2
—
OPERATION IN POWER-MANAGED
MODES
SAMPLING
OERR
TRMT
WUE
Bit 1
Baud Rate Formula
F
F
ABDEN
F
RX9D
OSC
OSC
TX9D
Bit 0
OSC
/[64 (n + 1)]
/[16 (n + 1)]
/[4 (n + 1)]
DS39635B-page 213
Reset Values
on Page
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