T89C5121-ICUIL Atmel, T89C5121-ICUIL Datasheet - Page 48

• Manufacturer Part Number: T89C5121-ICUIL
• Description: IC 8051 MCU W/SMART CARD 24SSOP
• Manufacturer: Atmel
• Series: 89Cr

Specifications of T89C5121-ICUIL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SmartCard, UART/USART
• Peripherals: LED, POR, WDT
• Number Of I /o: 14
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: Flash RAM
• Eeprom Size: 16K x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 5.4 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 24-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -
• Other names: Q1468934; T89C5121-ICSIL; T89C5121-ICSIL

INT1 Interrupt Vector
INT1/OE Input
Rxd Input
CPRES Input
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A/T8xC5121
A low-priority interrupt can be interrupted by a high priority interrupt, but not by another
low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt
source.
If two interrupt requests of different priority levels are received simultaneously, the
request of higher priority level is serviced. If interrupt requests of the same priority level
are received simultaneously, an internal polling sequence determines which request is
serviced. Thus within each priority level there is a second priority structure determined
by the polling sequence.
Table 31. Interrupt Vector Addresses
The INT1 interrupt is multiplexed with the three following inputs:
•
•
•
The setting configurations for each input is detailed below:
This interrupt input is active under the following conditions:
•
•
•
The Bit IE1 (TCON Register) is set by hardware when external interrupt detected. It is
cleared when interrupt is processed.
A second vector interrupt input is the reception of a character. UART Rx input can gen-
erate an interrupt if enabled with Bit RXEN (ISEL.0). The global enable bits EX1 and EA
must also be set.
Then, the Bit RXIT (ISEL Register) is set by hardware when a low level is detected on
P3.0/RXD input.
The third input is the detection of a level change on CPRES input (P1.2). This input can
generate an interrupt if enabled with PRESEN (ISEL.1), EX1 (IE0.2) and EA (IE0.7) Bits.
This detection is done according to the level selected with Bit CPLEV (ISEL.7).
Then the Bit PRESIT (ISEL.5) is set by hardware when the triggering conditions are
met. This Bit must be cleared by software.
INT1/OE: Standard 8051 interrupt input
Rxd: Received data on UART
CPRES: Insertion or removall of the main card
It must be enabled thanks to OEEN Bit (ISEL Register)
It can be active on a level or falling edge: thanks to IT1 Bit (TCON Register)
If level triggering selection is set, the active level 0 or 1 can be selected with OELEV
Bit (ISEL Register)
Interrupt Source
IE1 & RxIt & PrIt
RI & TI
TF0
TF1
SCI
IE0
Vector Address
000Bh
001Bh
0003h
0013h
0023h
0053h
4164G–SCR–07/06