PIC18F2510-I/SP Microchip Technology, PIC18F2510-I/SP Datasheet - Page 252

• Manufacturer Part Number: PIC18F2510-I/SP
• Description: IC MCU FLASH 16KX16 28-DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2510-I/SP

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 25
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Controller Family/series: PIC18
• No. Of I/o's: 25
• Ram Memory Size: 1.5KB
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F2X1X/4X1X
FIGURE 22-6:
TABLE 22-3:
DS39636D-page 254
300008h
300009h
30000Ah
30000Bh
30000Ch
30000Dh
Legend:
Note 1:
2:
File Name
Shaded cells are unimplemented.
Unimplemented in PIC18F2410/4410 devices; maintain this bit set.
Unimplemented in PIC18F2515/4515 devices; maintain this bit set.
(PIC18F2515/4515)
CONFIG5L
CONFIG5H
CONFIG6L
CONFIG6H
CONFIG7L
CONFIG7H
Unimplemented
SUMMARY OF CODE PROTECTION REGISTERS
48 Kbytes
Boot Block
Read ‘0’s
Block 0
Block 1
Block 2
MEMORY SIZE/DEVICE
CODE-PROTECTED PROGRAM MEMORY FOR PIC18F2515/2610/4515/4610
Bit 7
—
—
—
—
—
—
(PIC18F2610/4610)
Unimplemented
Boot Block
64 Kbytes
Read ‘0’s
EBTRB
WRTB
Block 0
Block 1
Block 2
Block 3
Bit 6
CPB
—
—
—
WRTC
Bit 5
—
—
—
—
—
000000h
0007FFh
000800h
003FFFh
004000h
007FFFh
008000h
00BFFFh
00C000h
00FFFFh
010000h
1FFFFFh
Address
Range
Bit 4
—
—
—
—
—
—
(Unimplemented Memory Space)
EBTR3
WRT3
CP3
Block Code Protection
Bit 3
—
—
—
CPB, WRTB, EBTRB
CP0, WRT0, EBTR0
CP1, WRT1, EBTR1
CP2, WRT2, EBTR2
CP3, WRT3, EBTR3
(1,2)
(1,2)
(1,2)
Controlled By:
EBTR2
WRT2
CP2
Bit 2
© 2009 Microchip Technology Inc.
—
—
—
(1)
(1)
(1)
EBTR1
WRT1
Bit 1
CP1
—
—
—
EBTR0
WRT0
Bit 0
CP0
—
—
—