PIC18F2510-I/SP Microchip Technology, PIC18F2510-I/SP Datasheet - Page 84

• Manufacturer Part Number: PIC18F2510-I/SP
• Description: IC MCU FLASH 16KX16 28-DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2510-I/SP

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 25
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Controller Family/series: PIC18
• No. Of I/o's: 25
• Ram Memory Size: 1.5KB
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F2X1X/4X1X
REGISTER 8-2:
DS39636D-page 86
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
INTCON2 REGISTER
bit 7
RBPU: PORTB Pull-up Enable bit
1 = All PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
INTEDG0: External Interrupt 0 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
INTEDG1: External Interrupt 1 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
INTEDG2: External Interrupt 2 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
Unimplemented: Read as ‘0’
TMR0IP: TMR0 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
Unimplemented: Read as ‘0’
RBIP: RB Port Change Interrupt Priority bit
1 = High priority
0 = Low priority
Legend:
R = Readable bit
-n = Value at POR
Note:
R/W-1
RBPU
Interrupt flag bits are set when an interrupt condition occurs regardless of the state
of its corresponding enable bit or the global interrupt enable bit. User software
should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt. This feature allows for software polling.
INTEDG0
R/W-1
INTEDG1
R/W-1
W = Writable bit
‘1’ = Bit is set
INTEDG2
R/W-1
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
—
TMR0IP
R/W-1
© 2009 Microchip Technology Inc.
x = Bit is unknown
U-0
—
R/W-1
RBIP
bit 0