T89C51CC02UA-RATIM Atmel, T89C51CC02UA-RATIM Datasheet - Page 23
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T89C51CC02UA-RATIM
Manufacturer Part Number
T89C51CC02UA-RATIM
Description
IC 8051 MCU FLASH 16K 32VQFP
Manufacturer
Atmel
Series
AT89C CANr
Datasheets
1.T89C51CC02CA-TDSIM.pdf
(159 pages)
2.T89C51CC02CA-TDSIM.pdf
(33 pages)
3.T89C51CC02CA-TDSIM.pdf
(29 pages)
4.T89C51CC02CA-TDSIM.pdf
(148 pages)
Specifications of T89C51CC02UA-RATIM
Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
20
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
For Use With
AT89STK-06 - KIT DEMOBOARD 8051 MCU W/CAN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
T89C51CC02UARATIM
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Exiting Power-down Mode
Figure 8. Power-down Exit Waveform Using INT1:0#
4126L–CAN–01/08
INT1:0#
OSC
Active phase
Note:
There are two ways to exit the Power-down mode:
1. Generate an enabled external interrupt.
Notes:
2. Generate a reset.
Notes:
–
–
Power-down phase
If
V
The A/T89C51CC02 provides capability to exit from Power-down using
INT0#, INT1#.
Hardware clears PD bit in PCON register which starts the oscillator and
restores the clocks to the CPU and peripherals. Using INTx# input,
execution resumes when the input is released (See Figure 8). Execution
resumes with the interrupt service routine. Upon completion of the interrupt
service routine, program execution resumes with the instruction immediately
following the instruction that activated Power-down mode.
1. The external interrupt used to exit Power-down mode must be configured as level
2. Exit from power-down by external interrupt does not affect the SFRs nor the internal
A logic high on the RST pin clears PD bit in PCON register directly and
asynchronously. This starts the oscillator and restores the clock to the CPU
and peripherals. Program execution momentarily resumes with the
instruction immediately following the instruction that activated Power-down
mode and may continue for a number of clock cycles before the internal
reset algorithm takes control. Reset initializes the A/T89C51CC02 and
vectors the CPU to address 0000h.
1. During the time that execution resumes, the internal RAM cannot be accessed; how-
2. Exit from power-down by reset redefines all the SFRs, but does not affect the internal
DD
V
sensitive (INT0# and INT1#) and must be assigned the highest priority. In addition,
the duration of the interrupt must be long enough to allow the oscillator to stabilize.
The execution will only resume when the interrupt is deasserted.
RAM content.
ever, it is possible for the Port pins to be accessed. To avoid unexpected outputs at
the Port pins, the instruction immediately following the instruction that activated the
Power-down mode should not write to a Port pin or to the external RAM.
RAM content.
DD
is restored to the normal operating level.
was reduced during the Power-down mode, do not exit Power-down mode until
Oscillator restart phase
Active phase
AT/T89C51CC02
23