DSPIC30F3014-30I/P Microchip Technology, DSPIC30F3014-30I/P Datasheet - Page 158

• Manufacturer Part Number: DSPIC30F3014-30I/P
• Description: IC DSPIC MCU/DSP 24K 40DIP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3014-30I/P

• Program Memory Type: FLASH
• Package / Case: 40-DIP (0.600", 15.24mm)
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 24KB (8K x 24)
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 40 MHz
• Operating Supply Voltage: 2.5 V to 5.5 V
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Data Rom Size: 1024 B
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC30F003 - MODULE SOCKET DSPIC30F 40DIPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLEACICE0206 - ADAPTER MPLABICE 40P 600 MIL
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F301430/P

TABLE 20-7:
TABLE 20-8:
RCON
OSCCON
OSCTUN
PMD1
PMD2
Legend:
Note
FOSC
FWDT
FBORPOR F80004
FBS
FSS
FGS
FICD
Legend:
Note
Name
SFR
Name
1:
2:
3:
4:
1:
2:
3:
4:
Addr.
0740
0742
0744
0770
0772
Address
F80000
F80002
F80006
F80008
F8000A
F8000C
— = unimplemented bit, read as ‘0’
Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
Reset state depends on type of Reset.
Reset state depends on Configuration bits.
These bits are not available in dsPIC30F3014 devices.
— = unimplemented bit, read as ‘0’
Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
These bits are reserved (read as ‘1’ and must be programmed as ‘1’).
Reserved bits read as ‘1’ and must be programmed as ‘1’.
The FGS<2> bit is a read-only copy of the GCP bit (FGS<1>).
IC8MD
T5MD
TRAPR
Bit 15
SYSTEM INTEGRATION REGISTER MAP
DEVICE CONFIGURATION REGISTER MAP
—
—
FWDTEN
MCLREN
BKBUG
(4)
Bit 15
(4)
FCKSM<1:0>
—
—
—
IOPUWR
IC7MD
T4MD
Bit 14
—
(4)
(4)
COSC<2:0>
Bit 14
COE
—
—
—
—
—
Bit 13
BGST LVDEN
T3MD
—
—
Bit 13
Bit 12 Bit 11
T2MD
—
—
—
—
—
Reserved
Reserved
—
—
T1MD
Bit 12
—
—
—
(3)
(3)
—
—
—
—
—
Bit 10
—
—
—
Bit 11
LVDL<3:0>
—
—
—
—
—
—
—
NOSC<2:0>
IC2MD
Bit 9
—
—
PWMPIN
(1)
Bit 10
—
—
—
—
—
(1)
DCIMD
IC1MD
Bit 8
(2)
—
FOS<2:0>
(4)
HPOL
Bit 9
I2CMD U2MD
—
—
—
—
EXTR
Bit 7
POST<1:0>
Reserved
—
—
(2)
Reserved
SWR SWDTEN WDTO
Bit 6
LPOL
—
—
Bit 8
(3)
—
—
—
(2)
(3)
LOCK
U1MD
Bit 5
—
—
BOREN
Bit 7
—
—
—
—
—
—
Bit 4
—
—
—
—
Bit 6
—
—
—
—
—
—
—
OC4MD
SPI1MD
SLEEP
TUN3
Bit 3
CF
(4)
Bit 5
—
FWPSA<1:0>
—
—
—
—
BORV<1:0>
OC3MD
TUN2
Bit 2
IDLE
—
—
Bit 4
(4)
—
—
—
—
LPOSCEN OSWEN
OC2MD
C1MD
TUN1
Bit 1
BOR
Bit 3
—
—
—
ADCMD 0000 0000 0000 0000
OC1MD 0000 0000 0000 0000
TUN0
Bit 0
POR
Reserved
FPR<4:0>
Bit 2
FWPSB<3:0>
—
—
Reserved
Reserved
0000 0000 0000 0000
(4)
Reset State
(3)
(3)
Bit 1
GCP
(Note 2)
(Note 3)
FPWRT<1:0>
ICS<1:0>
GWRP
Bit 0