DSPIC30F3014-30I/P Microchip Technology, DSPIC30F3014-30I/P Datasheet - Page 63

• Manufacturer Part Number: DSPIC30F3014-30I/P
• Description: IC DSPIC MCU/DSP 24K 40DIP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3014-30I/P

• Program Memory Type: FLASH
• Package / Case: 40-DIP (0.600", 15.24mm)
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 24KB (8K x 24)
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 40 MHz
• Operating Supply Voltage: 2.5 V to 5.5 V
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Data Rom Size: 1024 B
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC30F003 - MODULE SOCKET DSPIC30F 40DIPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLEACICE0206 - ADAPTER MPLABICE 40P 600 MIL
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F301430/P

Each hard trap that occurs must be Acknowledged
before code execution of any type may continue. If a
lower priority hard trap occurs while a higher priority
trap is pending, Acknowledged, or is being processed,
a hard trap conflict occurs.
The device is automatically Reset in a hard trap conflict
condition. The TRAPR status bit (RCON<15>) is set
when the Reset occurs so that the condition may be
detected in software.
FIGURE 8-1:
 2010 Microchip Technology Inc.
AIVT
IVT
Oscillator Fail Trap Vector
Address Error Trap Vector
Oscillator Fail Trap Vector
Address Error Trap Vector
Reset – GOTO Instruction
Stack Error Trap Vector
Stack Error Trap Vector
Reset – GOTO Address
Math Error Trap Vector
Math Error Trap Vector
Interrupt 52 Vector
Interrupt 53 Vector
Interrupt 52 Vector
Interrupt 53 Vector
Interrupt 0 Vector
Interrupt 1 Vector
Reserved Vector
Reserved Vector
Interrupt 0 Vector
Interrupt 1 Vector
Reserved Vector
Reserved Vector
Reserved Vector
Reserved Vector
TRAP VECTORS
Reserved
Reserved
Reserved
Reserved
—
—
—
—
—
—
0x000000
0x000002
0x000014
0x000094
0x0000FE
0x000004
0x00007E
0x000080
0x000082
0x000084
8.4
All interrupt event flags are sampled in the beginning of
each instruction cycle by the IFSx registers. A pending
Interrupt Request (IRQ) is indicated by the flag bit
being equal to a ‘1’ in an IFSx register. The IRQ causes
an interrupt to occur if the corresponding bit in the Inter-
rupt Enable (IECx) register is set. For the remainder of
the instruction cycle, the priorities of all pending
interrupt requests are evaluated.
If there is a pending IRQ with a priority level greater
than the current processor priority level in the IPL bits,
the processor is interrupted.
The processor then stacks the current program counter
and the low byte of the processor STATUS register
(SRL), as shown in
STATUS register contains the processor priority level at
the time prior to the beginning of the interrupt cycle.
The processor then loads the priority level for this
interrupt into the STATUS register. This action disables
all lower priority interrupts until the completion of the
Interrupt Service Routine.
FIGURE 8-2:
The RETFIE (return from interrupt) instruction unstacks
the program counter and STATUS registers to return
the processor to its state prior to the interrupt
sequence.
0x0000
dsPIC30F3014/4013
Note 1: The user can always lower the priority
2: The IPL3 bit (CORCON<3>) is always
Interrupt Sequence
15
SRL IPL3 PC<22:16>
level by writing a new value into SR. The
Interrupt Service Routine must clear the
interrupt flag bits in the IFSx register
before lowering the processor interrupt
priority, in order to avoid recursive
interrupts.
clear when interrupts are being pro-
cessed. It is set only during execution of
traps.
<Free Word>
PC<15:0>
INTERRUPT STACK FRAME
Figure
8-2. The low byte of the
0
POP : [--W15]
PUSH: [W15++]
W15 (before CALL)
W15 (after CALL)
DS70138G-page 63