PIC18F4423-I/PT Microchip Technology, PIC18F4423-I/PT Datasheet
PIC18F4423-I/PT
Specifications of PIC18F4423-I/PT
Available stocks
Related parts for PIC18F4423-I/PT
PIC18F4423-I/PT Summary of contents
Page 1
... Flash Microcontroller Programming Specification 1.0 DEVICE OVERVIEW This document includes the programming specifications for the following devices: • PIC18F2423 • PIC18F4423 • PIC18F2523 • PIC18F4523 2.0 PROGRAMMING OVERVIEW PIC18F2423/2523/4423/4523 devices programmed using either the high-voltage In-Circuit Serial Programming™ (ICSP™) method or the low-voltage ICSP method. Both methods can be done with the device in the users’ ...
Page 2
... RB7/PGD RB6/PGC RB5/PGM RB4 RB3 RB2 RB1 RB0 RC7 RC6 RC5 RC4 RB3 RB2 RB1 RB0 RC7 RB7/PGD RB6/PGC RB5/PGM RB4 RB3 RB2 RB1 RB0 RD7 RD6 RD5 RD4 RC7 RC6 RC5 RC4 RD3 RD2 © 2005 Microchip Technology Inc. ...
Page 3
... RC7 RD4 RD5 RD6 RD7 RB0 RB1 RB2 © 2005 Microchip Technology Inc. PIC18F2423/2523/4423/4523 ICV RC0 2 OSC2 OSC1 PIC18F4423 PIC18F4523 27 RE2 RE1 RE0 RA5 RA4 OSC2 1 33 OSC1 PIC18F4423 PIC18F4523 RE2 27 7 RE1 8 26 RE0 9 25 RA5 24 10 RA4 23 11 DS39759A-page 3 ...
Page 4
... Code Memory Size (Bytes) PIC18F2523 000000h-007FFFh (32K) PIC18F4523 MEMORY SIZE/DEVICE 32 Kbytes Address (PIC18F2523/4523) Range 000000h Boot Block 0007FFh 000800h Block 0 001FFFh 002000h Block 1 003FFFh 004000h Block 2 005FFFh 006000h Block 3 007FFFh 008000h Unimplemented Reads all ‘0’s 1FFFFFh © 2005 Microchip Technology Inc. ...
Page 5
... Space 3FFFFFh Note: Sizes of memory areas are not to scale. © 2005 Microchip Technology Inc. PIC18F2423/2523/4423/4523 TABLE 2-3: IMPLEMENTATION OF CODE MEMORY Device PIC18F2423 PIC18F4423 MEMORY SIZE/DEVICE 16 Kbytes (PIC18F2423/4423) Boot Block Block 0 Block 1 008000h Unimplemented Reads all ‘0’s Code Memory Size (Bytes) ...
Page 6
... ID Location 8 CONFIG1L CONFIG1H CONFIG2L CONFIG2H CONFIG3L CONFIG3H CONFIG4L CONFIG4H CONFIG5L CONFIG5H CONFIG6L CONFIG6H CONFIG7L CONFIG7H Device ID1 Device ID2 © 2005 Microchip Technology Inc. TBLPTRL Addr[7:0] 200000h 200001h 200002h 200003h 200004h 200005h 200006h 200007h 300000h 300001h 300002h 300003h 300004h 300005h 300006h ...
Page 7
... Verify Configuration Bits Done Note 1: Selected devices only, see Section 3.3 “Data EEPROM Programming”. © 2005 Microchip Technology Inc. PIC18F2423/2523/4423/4523 2.5 Entering and Exiting High-Voltage ICSP Program/Verify Mode As shown in Figure 2-7, the High-Voltage ICSP Program/Verify mode is entered by holding PGC and PGD low and then raising MCLR/V (high voltage) ...
Page 8
... Table Write, start programming TABLE 2-5: 4-Bit Command 1101 COMMANDS FOR PROGRAMMING 4-Bit Description Command 0000 0010 1000 1001 1010 1011 1100 1101 1110 1111 SAMPLE COMMAND SEQUENCE Data Core Instruction Payload 3C 40 Table Write, post-increment by 2 © 2005 Microchip Technology Inc. ...
Page 9
... FIGURE 2-11: TABLE WRITE, POST-INCREMENT TIMING (1101) P2 P2A P2B PGC PGD 4-Bit Command © 2005 Microchip Technology Inc. PIC18F2423/2523/4423/4523 16-Bit Data Payload PGD = Input P5A Fetch Next 4-Bit Command DS39759A-page 9 ...
Page 10
... F6 MOVWF TBLPTRL 87 87 Write 8787h TO 3C0004h to erase entire device NOP 00 00 Hold PGD low until erase completes. BULK ERASE FLOW Start Write 0F0Fh to 3C0005h Write 8787h to 3C0004h to Erase Entire Device Delay P11 + P10 Time Done © 2005 Microchip Technology Inc. ...
Page 11
... Section 3.3 “Data EEPROM Programming”) must be performed at a supply voltage below the Bulk Erase limit, follow the methodology described in Section 3.3 EEPROM Programming” and write ‘1’s to the array. © 2005 Microchip Technology Inc. PIC18F2423/2523/4423/4523 ...
Page 12
... NOP – hold PGC high for time P9 and low for time P10. Start Configure Device for Row Erases Start Erase Sequence and Hold PGC High for Time P9 Hold PGC Low for Time P10 All No rows done? Yes Done Addr = 0 © 2005 Microchip Technology Inc. ...
Page 13
... The TBLPTR register must point to the same region when initiating the program- ming sequence as it did when the write buffers were loaded. TABLE 3-4: Devices PIC18F2423 PIC18F2523 PIC18F4423 PIC18F4523 Core Instruction BSF EECON1, EEPGD BCF EECON1, CFGS MOVLW <Addr[21:16]> MOVWF TBLPTRU MOVLW < ...
Page 14
... Yes Start Write Sequence and Hold PGC High until Done and Wait P9 Hold PGC Low for Time P10 All No locations done? Yes Done P5A 4-Bit Command PGD = Input P10 16-Bit Programming Time Data Payload © 2005 Microchip Technology Inc. ...
Page 15
... Table 3-4) at each iteration of the loop. The write cycle must be repeated enough times to completely rewrite the contents of the erase buffer. Step 7: Disable writes. 0000 94 A6 © 2005 Microchip Technology Inc. PIC18F2423/2523/4423/4523 The appropriate number of bytes required for the erase buffer must be read out of code memory (as described in Section 4.2 “Verify Code Memory and ID Locations” ...
Page 16
... MOVF EECON1 PGD = Input PROGRAM DATA FLOW Start Set Address Set Data Enable Write Start Write Sequence No WR bit clear? Yes No Done? Yes Done P10 16-Bit Data Payload P5A Shift Out Data (see Figure 4-4) PGD = Output © 2005 Microchip Technology Inc. ...
Page 17
... Step 7: Hold PGC low for time P10. Step 8: Disable writes. 0000 94 A6 Repeat steps 2 through 8 to write more data. Note 1: See Figure 4-4 for details on shift out data timing. © 2005 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Core Instruction BCF EECON1, EEPGD BCF ...
Page 18
... MOVWF TBLPTRL Write 2 bytes and post-increment address by 2. Write 2 bytes and post-increment address by 2. Write 2 bytes and post-increment address by 2. Write 2 bytes and start programming. NOP - hold PGC high for time P9 and low for time P10. © 2005 Microchip Technology Inc. ...
Page 19
... Address Program LSB Delay P9 and P10 Time for Write Done © 2005 Microchip Technology Inc. PIC18F2423/2523/4423/4523 3.6 Configuration Bits Programming Unlike code memory, the Configuration bits are programmed a byte at a time. The Table Write, Begin Programming 4-bit command (‘1111’) is used, but only 8 bits of the following 16-bit payload will be written ...
Page 20
... ID and Configuration registers. Core Instruction MOVLW Addr[21:16] MOVWF TBLPTRU MOVLW <Addr[15:8]> MOVWF TBLPTRH MOVLW <Addr[7:0]> MOVWF TBLPTRL TBLRD *+ P14 LSb Shift Data Out PGD = Output P5A MSb Fetch Next 4-Bit Command PGD = Input © 2005 Microchip Technology Inc. ...
Page 21
... Yes All No code memory verified? Yes © 2005 Microchip Technology Inc. PIC18F2423/2523/4423/4523 The Table Pointer must be manually set to 200000h (base address of the ID locations) once the code memory has been verified. The post-increment feature of the table read 4-bit command may not be used to increment the Table Pointer beyond the code memory space ...
Page 22
... EECON1, CFGS MOVLW <Addr> MOVWF EEADR MOVLW <AddrH> MOVWF EEADRH BSF EECON1, RD MOVF EEDATA MOVWF TABLAT NOP (1) Shift Out Data READ DATA EEPROM FLOW Start Set Address Read Byte Move to TABLAT Shift Out Data No Done? Yes Done © 2005 Microchip Technology Inc. ...
Page 23
... Given that Blank Checking is merely code and data EEPROM verification with FFh expect data, refer to Section 4.4 “Read Data EEPROM Memory” and Section 4.2 “Verify Code Memory and ID Locations” for implementation details. © 2005 Microchip Technology Inc. PIC18F2423/2523/4423/4523 ...
Page 24
... Unimplemented in PIC18F2423/4423 devices; maintain this bit set. 2: DEVID registers are read-only and cannot be programmed by the user. TABLE 5-2: DEVICE ID VALUE Device PIC18F2423 PIC18F2523 PIC18F4423 PIC18F4523 Note: The ‘x’s in DEVID1 contain the device revision code. DS39759A-page 24 5.2 Device ID Word The device ID word for the PIC18F2423/2523/4423/ ...
Page 25
... BOREN1:BOREN0 CONFIG2L PWRTEN CONFIG2L WDPS3:WDPS0 CONFIG2H WDTEN CONFIG2H © 2005 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Description Internal External Switchover bit 1 = Internal External Switchover mode enabled 0 = Internal External Switchover mode disabled Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor enabled 0 = Fail-Safe Clock Monitor disabled ...
Page 26
... Code Protection bits (Data EEPROM Data EEPROM is not code-protected 0 = Data EEPROM is code-protected Code Protection bits (Boot Block memory area Boot Block is not code-protected 0 = Boot Block is code-protected Write Protection bits (Block 3 code memory area Block 3 is not write-protected 0 = Block 3 is write-protected © 2005 Microchip Technology Inc. ...
Page 27
... EBTRB CONFIG7H DEV11:DEV4 DEVID2 DEV3:DEV0 DEVID1 REV3:REV0 DEVID1 © 2005 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Description Write Protection bits (Block 2 code memory area Block 2 is not write-protected 0 = Block 2 is write-protected Write Protection bits (Block 1 code memory area Block 1 is not write-protected 0 = Block 1 is write-protected ...
Page 28
... EEPROM information must be included. An option to not include the data EEPROM information may be provided. When embedding data EEPROM information in the hex file, it should start at address F00000h. Microchip Technology Inc. believes that this feature is important for the benefit of the end customer. DS39759A-page 28 5.6 Checksum Computation The checksum is calculated by summing the following: • ...
Page 29
... Legend: — = unimplemented. TABLE 5-5: CONFIGURATION WORD MASKS FOR COMPUTING CHECKSUMS Device PIC18F2423 PIC18F2523 PIC18F4423 PIC18F4523 Legend: Shaded cells are unimplemented. © 2005 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Ending Address Block 0 Block 1 Block 2 Block 3 001FFF 003FFF — — 001FFF 003FFF ...
Page 30
... V (Note 2) V Externally timed, row erases and all writes V Self-timed, bulk erases only (Note 3) μA (Note meet AC specifications μs (Note 5.0V DD μ Externally timed μ the oscillator period. For OSC © 2005 Microchip Technology Inc. ...
Page 31
... T is the instruction cycle time specific values, refer to the Electrical Characteristics section of the device data sheet for the particular device. 2: When ICPORT = 1, this specification also applies to ICV 3: At 0°C-50°C. © 2005 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Min Max 4 /RE3 ↑ /RE3 ↑ ...
Page 32
... PIC18F2423/2523/4423/4523 NOTES: DS39759A-page 32 © 2005 Microchip Technology Inc. ...
Page 33
... PowerMate, PowerTool, Real ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and Zena are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
Page 34
... Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2005 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-399 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...