PIC18F4423-I/PT Microchip Technology, PIC18F4423-I/PT Datasheet - Page 10

• Manufacturer Part Number: PIC18F4423-I/PT
• Description: IC PIC MCU FLASH 8KX16 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4423-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 16KB (8K x 16)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163022, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 13-ch x 12-bit
• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• Rohs Compliant: Yes
• Package: 44TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 444-1001 - DEMO BOARD FOR PICMICRO MCUAC164020 - MODULE SKT PROMATEII 44TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F2423/2523/4423/4523
3.0
Programming includes the ability to erase or write the
various memory regions within the device.
In all cases except high-voltage ICSP Bulk Erase, the
EECON1 register must be configured in order to
operate on a particular memory region.
When using the EECON1 register to act on code
memory, the EEPGD bit must be set (EECON1<7> = 1)
and the CFGS bit must be cleared (EECON1<6> = 0).
The WREN bit must be set (EECON1<2> = 1) to
enable writes of any sort (e.g., erases) and this must be
done prior to initiating a write sequence. The FREE bit
must be set (EECON1<4> = 1) in order to erase the
program space being pointed to by the Table Pointer.
The erase or write sequence is initiated by setting the
WR bit (EECON1<1> = 1). It is strongly recommended
that the WREN bit only be set immediately prior to a
program erase.
3.1
3.1.1
Erasing code or data EEPROM is accomplished by
configuring two Bulk Erase Control registers located at
3C0004h and 3C0005h. Code memory may be erased
portions at a time, or the user may erase the entire
device in one action. Bulk Erase operations will also
clear any code-protect settings associated with the
memory block erased. Erase options are detailed in
Table 3-1.
(CPD = 0), the user must request an erase of data
EEPROM (e.g., 0084h as shown in Table 3-1).
TABLE 3-1:
The actual Bulk Erase function is a self-timed
operation. Once the erase has started (falling edge of
the 4th PGC after the NOP command), serial execution
will cease until the erase completes (parameter P11).
During this time, PGC may continue to toggle but PGD
must be held low.
DS39759A-page 10
Chip Erase
Erase Data EEPROM
Erase Boot Block
Erase Config Bits
Erase Code EEPROM Block 0
Erase Code EEPROM Block 1
Erase Code EEPROM Block 2
Erase Code EEPROM Block 3
Note 1:
DEVICE PROGRAMMING
ICSP Erase
Description
Selected devices only, see Section 3.3
“Data EEPROM Programming”.
HIGH-VOLTAGE ICSP BULK ERASE
If
data
BULK ERASE OPTIONS
(1)
EEPROM
(3C0005h:3C0004h)
is
code-protected
0F87h
0084h
0081h
0082h
0180h
0280h
0480h
0880h
Data
The code sequence to erase the entire device is shown
in Table 3-2 and the flowchart is shown in Figure 3-1.
TABLE 3-2:
FIGURE 3-1:
Command
Note:
0000
0000
0000
0000
0000
0000
1100
0000
0000
0000
0000
0000
0000
1100
0000
0000
4-Bit
A Bulk Erase is the only way to reprogram
code-protect bits from an ON state to an
OFF state.
Payload
0E 3C
6E F8
0E 00
6E F7
0E 05
6E F6
0F 0F
0E 3C
6E F8
0E 00
6E F7
0E 04
6E F6
87 87
00 00
00 00
Data
BULK ERASE COMMAND
SEQUENCE
3C0004h to Erase
Delay P11 + P10
Write 8787h to
Entire Device
Write 0F0Fh
to 3C0005h
BULK ERASE FLOW
© 2005 Microchip Technology Inc.
Done
MOVLW 3Ch
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 05h
MOVWF TBLPTRL
Write 0Fh to 3C0005h
MOVLW 3Ch
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 04h
MOVWF TBLPTRL
Write 8787h TO 3C0004h
to erase entire
device.
NOP
Hold PGD low until
erase completes.
Time
Start
Core Instruction