PIC18F2455-I/SP Microchip Technology, PIC18F2455-I/SP Datasheet
PIC18F2455-I/SP
Specifications of PIC18F2455-I/SP
Available stocks
Related parts for PIC18F2455-I/SP
PIC18F2455-I/SP Summary of contents
Page 1
... PIC18F2455/2550/4455/4550 28/40/44-Pin, High-Performance, Enhanced Flash, USB Microcontrollers © 2009 Microchip Technology Inc. Data Sheet with nanoWatt Technology DS39632E ...
Page 2
... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
Page 3
... PIC18F4550 32K 16384 2048 © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Peripheral Highlights: • High-Current Sink/Source: 25 mA/25 mA • Three External Interrupts • Four Timer modules (Timer0 to Timer3) • Capture/Compare/PWM (CCP) modules: - Capture is 16-bit, max. resolution 5 Compare is 16-bit, max. resolution 83 PWM output: PWM resolution 10-bit • ...
Page 4
... PIC18F2455/2550/4455/4550 Pin Diagrams 28-Pin PDIP, SOIC MCLR/V /RE3 PP RA0/AN0 RA1/AN1 RA2/AN2/V -/CV REF RA3/AN3/V REF RA4/T0CKI/C1OUT/RCV RA5/AN4/SS/HLVDIN/C2OUT V OSC1/CLKI OSC2/CLKO/RA6 RC0/T1OSO/T13CKI (1) RC1/T1OSI/CCP2 /UOE RC2/CCP1 V 40-Pin PDIP MCLR/V /RE3 PP RA0/AN0 RA1/AN1 RA2/AN2/V -/CV REF RA3/AN3/V REF RA4/T0CKI/C1OUT/RCV RA5/AN4/SS/HLVDIN/C2OUT RE0/AN5/CK1SPP RE1/AN6/CK2SPP RE2/AN7/OESPP V V OSC1/CLKI OSC2/CLKO/RA6 RC0/T1OSO/T13CKI ...
Page 5
... RB1/AN10/INT1/SCK/SCL RB2/AN8/INT2/VMO Note 1: RB3 is the alternate pin for CCP2 multiplexing. 2: Special ICPORT features available in select circumstances. See Section 25.9 “Special ICPORT Features (44-Pin TQFP Package Only)” for more information. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 33 NC/ICRST 1 32 RC0/T1OSO/T13CKI 2 31 OSC2/CLKO/RA6 ...
Page 6
... Appendix E: Migration From Mid-Range to Enhanced Devices ......................................................................................................... 421 Appendix F: Migration From High-End to Enhanced Devices............................................................................................................ 421 Index .................................................................................................................................................................................................. 423 The Microchip Web Site ..................................................................................................................................................................... 433 Customer Change Notification Service .............................................................................................................................................. 433 Customer Support .............................................................................................................................................................................. 433 Reader Response .............................................................................................................................................................................. 434 PIC18F2455/2550/4455/4550 Product Identification System ............................................................................................................ 435 DS39632E-page 4 © 2009 Microchip Technology Inc. ...
Page 7
... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 DS39632E-page 5 ...
Page 8
... PIC18F2455/2550/4455/4550 NOTES: DS39632E-page 6 © 2009 Microchip Technology Inc. ...
Page 9
... Microchip Technology Inc. PIC18F2455/2550/4455/4550 1.1.3 MULTIPLE OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC18F2455/2550/4455/4550 family offer twelve different oscillator options, allowing users a wide range of choices in developing application hardware. These include: • Four Crystal modes using crystals or ceramic resonators. ...
Page 10
... DS39632E-page 8 1.3 Details on Individual Family Members Devices in the PIC18F2455/2550/4455/4550 family are available in 28-pin and 40/44-pin packages. Block diagrams for the two groups are shown in Figure 1-1 and Figure 1-2. The devices are differentiated from each other in six ways: 1 ...
Page 11
... Stack Underflow (PWRT, OST), MCLR (optional), Programmable Low-Voltage Detect Programmable Brown-out Reset Instruction Set 75 Instructions; 83 with Extended Instruction Set Packages © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 PIC18F2455 PIC18F2550 DC – 48 MHz DC – 48 MHz 24576 32768 12288 16384 2048 2048 256 256 19 19 ...
Page 12
... PIC18F2455/2550/4455/4550 FIGURE 1-1: PIC18F2455/2550 (28-PIN) BLOCK DIAGRAM Table Pointer<21> 8 inc/dec logic PCLATU PCLATH 21 20 PCU PCH PCL Program Counter 31 Level Stack Address Latch Program Memory STKPTR (24/32 Kbytes) Data Latch 8 Table Latch ROM Latch Instruction Bus <16> IR Instruction State Machine Decode & ...
Page 13
... These pins are only available on 44-pin TQFP packages under certain conditions. Refer to Section 25.9 “Special ICPORT Features (44-Pin TQFP Package Only)” for additional information. 4: RB3 is the alternate pin for CCP2 multiplexing. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Data Bus<8> Data Latch 8 Data Memory ...
Page 14
... PIC18F2455/2550/4455/4550 TABLE 1-2: PIC18F2455/2550 PINOUT I/O DESCRIPTIONS Pin Number Pin Name Type PDIP, SOIC MCLR/V /RE3 1 PP MCLR V PP RE3 OSC1/CLKI 9 OSC1 CLKI OSC2/CLKO/RA6 10 OSC2 CLKO RA6 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared. ...
Page 15
... TABLE 1-2: PIC18F2455/2550 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Type PDIP, SOIC RA0/AN0 2 RA0 AN0 RA1/AN1 3 RA1 AN1 RA2/AN2/V -/CV 4 REF REF RA2 AN2 V - REF CV REF RA3/AN3 REF RA3 AN3 V + REF RA4/T0CKI/C1OUT/RCV 6 RA4 T0CKI C1OUT RCV RA5/AN4/SS/ 7 HLVDIN/C2OUT RA5 ...
Page 16
... PIC18F2455/2550/4455/4550 TABLE 1-2: PIC18F2455/2550 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Type PDIP, SOIC RB0/AN12/INT0/FLT0/ 21 SDI/SDA RB0 AN12 INT0 FLT0 SDI SDA RB1/AN10/INT1/SCK/ 22 SCL RB1 AN10 INT1 SCK SCL RB2/AN8/INT2/VMO 23 RB2 AN8 INT2 VMO RB3/AN9/CCP2/VPO 24 RB3 AN9 (1) CCP2 VPO RB4/AN11/KBI0 ...
Page 17
... TABLE 1-2: PIC18F2455/2550 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Type PDIP, SOIC RC0/T1OSO/T13CKI 11 RC0 T1OSO T13CKI RC1/T1OSI/CCP2/UOE 12 RC1 T1OSI (2) CCP2 UOE RC2/CCP1 13 RC2 CCP1 RC4/D-/VM 15 RC4 D- VM RC5/D+/VP 16 RC5 D+ VP RC6/TX/CK 17 RC6 TX CK RC7/RX/DT/SDO 18 RC7 RX DT SDO RE3 — ...
Page 18
... PIC18F2455/2550/4455/4550 TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS Pin Number Pin Name PDIP QFN TQFP MCLR/V /RE3 MCLR V PP RE3 OSC1/CLKI 13 32 OSC1 CLKI OSC2/CLKO/RA6 14 33 OSC2 CLKO RA6 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared ...
Page 19
... Default assignment for CCP2 when CCP2MX Configuration bit is set. 3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No Connect unless ICPRT is set and the DEBUG Configuration bit is cleared. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Pin Buffer Type Type PORTA is a bidirectional I/O port ...
Page 20
... PIC18F2455/2550/4455/4550 TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP QFN TQFP RB0/AN12/INT0 FLT0/SDI/SDA RB0 AN12 INT0 FLT0 SDI SDA RB1/AN10/INT1/SCK SCL RB1 AN10 INT1 SCK SCL RB2/AN8/INT2/VMO 35 11 RB2 AN8 INT2 VMO RB3/AN9/CCP2/VPO 36 12 RB3 AN9 (1) CCP2 ...
Page 21
... Default assignment for CCP2 when CCP2MX Configuration bit is set. 3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No Connect unless ICPRT is set and the DEBUG Configuration bit is cleared. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Pin Buffer Type Type PORTC is a bidirectional I/O port ...
Page 22
... PIC18F2455/2550/4455/4550 TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP QFN TQFP RD0/SPP0 19 38 RD0 SPP0 RD1/SPP1 20 39 RD1 SPP1 RD2/SPP2 21 40 RD2 SPP2 RD3/SPP3 22 41 RD3 SPP3 RD4/SPP4 27 2 RD4 SPP4 RD5/SPP5/P1B 28 3 RD5 SPP5 P1B RD6/SPP6/P1C ...
Page 23
... Default assignment for CCP2 when CCP2MX Configuration bit is set. 3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No Connect unless ICPRT is set and the DEBUG Configuration bit is cleared. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Pin Buffer Type Type PORTE is a bidirectional I/O port ...
Page 24
... PIC18F2455/2550/4455/4550 NOTES: DS39632E-page 22 © 2009 Microchip Technology Inc. ...
Page 25
... They are discussed later in this chapter. 2.1.1 OSCILLATOR CONTROL The operation of the oscillator in PIC18F2455/2550/ 4455/4550 devices is controlled through two Configu- ration registers and two control registers. Configuration registers, CONFIG1L and CONFIG1H, select the oscillator mode and USB prescaler/postscaler options. ...
Page 26
... PIC18F2455/2550/4455/4550 FIGURE 2-1: PIC18F2455/2550/4455/4550 CLOCK DIAGRAM Primary Oscillator OSC2 Sleep OSC1 XT, HS, EC, ECIO Secondary Oscillator T1OSO T1OSCEN Enable Oscillator T1OSI Internal Oscillator Block 8 MHz Source 8 MHz (INTOSC) INTRC Source 31 kHz (INTRC) DS39632E-page 24 PIC18F2455/2550/4455/4550 PLLDIV ÷ 12 111 ÷ 10 110 USBDIV ÷ 6 101 ...
Page 27
... A series resistor (R ) may be required for AT S strip cut crystals varies with the oscillator mode chosen. F © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 TABLE 2-1: Typical Capacitor Values Used: Mode XT HS 16.0 MHz Capacitor values are for design guidance only. These capacitors were tested with the resonators listed below for basic start-up and operation ...
Page 28
... PIC18F2455/2550/4455/4550 TABLE 2-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Typical Capacitor Values Crystal Tested: Osc Type Freq MHz MHz MHz MHz 15 pF Capacitor values are for design guidance only. These capacitors were tested with the crystals listed below for basic start-up and operation. These values are not optimized ...
Page 29
... PLL FREQUENCY MULTIPLIER PIC18F2455/2550/4255/4550 devices include a Phase Locked Loop (PLL) circuit. This is provided specifically for USB applications with lower speed oscillators and can also be used as a microcontroller clock source. The PLL is enabled in HSPLL, XTPLL, ECPLL and ECPIO Oscillator modes designed to produce a fixed 96 MHz reference clock from a fixed 4 MHz input ...
Page 30
... PIC18F2455/2550/4455/4550 2.2.5.2 OSCTUNE Register The internal oscillator’s output has been calibrated at the factory but can be adjusted in the user’s applica- tion. This is done by writing to the OSCTUNE register (Register 2-1). The tuning sensitivity is constant throughout the tuning range. The INTOSC clock will stabilize within 1 ms. Code exe- cution continues during this shift ...
Page 31
... To adjust for this, decrement the OSCTUNE register. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Finally, a CCP module can use free-running Timer1 (or Timer3), clocked by the internal oscillator block and an external event with a known period (i.e., AC power frequency) ...
Page 32
... PIC18F2455/2550/4455/4550 2.3 Oscillator Settings for USB When these devices are used for USB connectivity, they must have either a 6 MHz or 48 MHz clock for USB operation, depending on whether Low-Speed or Full-Speed mode is being used. This may require some forethought in selecting an oscillator frequency and programming the device ...
Page 33
... Bold is used to highlight clock selections that are compatible with low-speed USB operation (system clock of 24 MHz, USB clock of 6 MHz). Note 1: Only valid when the USBDIV Configuration bit is cleared. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Clock Mode MCU Clock Division (FOSC3:FOSC0) (CPUDIV1:CPUDIV0) ...
Page 34
... OSC1 or OSC2 pins. These sources may continue to operate even after the controller is placed in a power-managed mode. PIC18F2455/2550/4455/4550 devices offer the Timer1 oscillator as a secondary oscillator. This oscillator, in all power-managed modes, is often the time base for functions such as a Real-Time Clock (RTC). Most often ...
Page 35
... OSCILLATOR TRANSITIONS PIC18F2455/2550/4455/4550 devices contain circuitry to prevent clock “glitches” when switching between clock sources. A short pause in the device clock occurs during the clock switch. The length of this pause is the REGISTER 2-2: OSCCON: OSCILLATOR CONTROL REGISTER R/W-0 R/W-1 R/W-0 IDLEN ...
Page 36
... PIC18F2455/2550/4455/4550 2.5 Effects of Power-Managed Modes on the Various Clock Sources When PRI_IDLE mode is selected, the designated primary oscillator continues to run without interruption. For all other power-managed modes, the oscillator using the OSC1 pin is disabled. Unless the USB module is enabled, the OSC1 pin (and OSC2 pin if used by the oscillator) will stop oscillating ...
Page 37
... POWER-MANAGED MODES PIC18F2455/2550/4455/4550 devices offer a total of seven operating modes for more efficient power management. These modes provide a variety of options for selective power conservation in applications where resources may be limited (i.e., battery-powered devices). There are three categories of power-managed modes: • Run modes • ...
Page 38
... PIC18F2455/2550/4455/4550 3.1.3 CLOCK TRANSITIONS AND STATUS INDICATORS The length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Three bits indicate the current clock source and its status. They are: • ...
Page 39
... PLL 2: Clock transition typically occurs within 2-4 T © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 On transitions from SEC_RUN mode to PRI_RUN, the peripherals and CPU continue to be clocked from the Timer1 oscillator while the primary clock is started. When the primary clock becomes ready, a clock switch back to the primary clock occurs (see Figure 3-2) ...
Page 40
... PIC18F2455/2550/4455/4550 3.2.3 RC_RUN MODE In RC_RUN mode, the CPU and peripherals are clocked from the internal oscillator block using the INTOSC multiplexer; the primary clock is shut down. When using the INTRC source, this mode provides the best power conservation of all the Run modes while still executing code ...
Page 41
... Multiplexer OSC1 T OST PLL Clock Output CPU Clock Peripheral Clock Program Counter SCS1:SCS0 bits Changed Note 1024 OST OSC PLL 2: Clock transition typically occurs within 2-4 T © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 n-1 n (1) Clock Transition OSC (1) PLL ( n-1 n (2) Clock ...
Page 42
... Sleep Mode The power-managed Sleep mode PIC18F2455/2550/4455/4550 devices is identical to the legacy Sleep mode offered in all other PIC devices entered by clearing the IDLEN bit (the default state on device Reset) and executing the SLEEP instruction. This shuts down the selected oscillator (Figure 3-5). All clock source status bits are cleared ...
Page 43
... Peripheral Clock Program Counter Wake Event © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 3.4.2 SEC_IDLE MODE In SEC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the Timer1 oscillator. This mode is entered from SEC_RUN by set- ting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, set IDLEN first, then set SCS1:SCS0 to ‘ ...
Page 44
... PIC18F2455/2550/4455/4550 3.4.3 RC_IDLE MODE In RC_IDLE mode, the CPU is disabled but the periph- erals continue to be clocked from the internal oscillator block using the INTOSC multiplexer. This mode allows for controllable power conservation during Idle periods. From RC_RUN, this mode is entered by setting the IDLEN bit and executing a SLEEP instruction ...
Page 45
... F12, Table 28-9 also designated Execution continues during T © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 In these instances, the primary clock source either does not require an oscillator start-up delay, since it is already running (PRI_IDLE), or normally does not require an oscillator start-up delay (EC and any internal oscillator modes) ...
Page 46
... PIC18F2455/2550/4455/4550 NOTES: DS39632E-page 44 © 2009 Microchip Technology Inc. ...
Page 47
... RESET The PIC18F2455/2550/4455/4550 devices differentiate between various kinds of Reset: a) Power-on Reset (POR) b) MCLR Reset during normal operation c) MCLR Reset during power-managed modes d) Watchdog Timer (WDT) Reset (during execution) e) Programmable Brown-out Reset (BOR) f) RESET Instruction g) Stack Full Reset h) Stack Underflow Reset ...
Page 48
... PIC18F2455/2550/4455/4550 REGISTER 4-1: RCON: RESET CONTROL REGISTER (1) R/W-0 R/W-1 U-0 IPEN SBOREN — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) ...
Page 49
... MCLR Reset path which detects and ignores small pulses. The MCLR pin is not driven low by any internal Resets, including the WDT. In PIC18F2455/2550/4455/4550 devices, the MCLR input can be disabled with the MCLRE Configuration bit. When MCLR is disabled, the pin becomes a digital input. See Section 10.5 “PORTE, TRISE and LATE Registers” ...
Page 50
... PIC18F2455/2550/4455/4550 4.4 Brown-out Reset (BOR) PIC18F2455/2550/4455/4550 devices implement a BOR circuit that provides the user with a number of configuration and power-saving options. The BOR is controlled by the BORV1:BORV0 BOREN1:BOREN0 Configuration bits. There are a total of four BOR configurations which are summarized in Table 4-1. The BOR threshold is set by the BORV1:BORV0 bits. If BOR is enabled (any values of BOREN1:BOREN0 except ‘ ...
Page 51
... Oscillator Start-up Timer (OST) • PLL Lock Time-out 4.5.1 POWER-UP TIMER (PWRT) The Power-up Timer (PWRT) of the PIC18F2455/2550/ 4455/4550 devices is an 11-bit counter which uses the INTRC source as the clock input. This yields an approximate time interval of 2048 x 32 μs = 65.6 ms. ...
Page 52
... PIC18F2455/2550/4455/4550 FIGURE 4-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 4-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO V ...
Page 53
... TIME-OUT SEQUENCE ON POR w/PLL ENABLED (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note 1024 clock cycles. OST ≈ max. First three stages of the Power-up Timer. T PLL © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 , V RISE > PWRT T OST T PWRT T OST T ...
Page 54
... PIC18F2455/2550/4455/4550 4.6 Reset State of Registers Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a “Reset state” depending on the type of Reset that occurred. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal oper- ation ...
Page 55
... See Table 4-3 for Reset value for specific condition. 5: PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 MCLR Resets, Power-on Reset, WDT Reset, Brown-out Reset ...
Page 56
... PIC18F2455/2550/4455/4550 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices INDF2 2455 2550 4455 4550 POSTINC2 2455 2550 4455 4550 POSTDEC2 2455 2550 4455 4550 PREINC2 2455 2550 4455 4550 PLUSW2 2455 2550 4455 4550 FSR2H 2455 2550 4455 4550 ...
Page 57
... See Table 4-3 for Reset value for specific condition. 5: PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 MCLR Resets, Power-on Reset, WDT Reset, Brown-out Reset ...
Page 58
... PIC18F2455/2550/4455/4550 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices IPR2 2455 2550 4455 4550 PIR2 2455 2550 4455 4550 PIE2 2455 2550 4455 4550 IPR1 2455 2550 4455 4550 2455 2550 4455 4550 PIR1 2455 2550 4455 4550 ...
Page 59
... See Table 4-3 for Reset value for specific condition. 5: PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 MCLR Resets, Power-on Reset, WDT Reset, Brown-out Reset ...
Page 60
... PIC18F2455/2550/4455/4550 NOTES: DS39632E-page 58 © 2009 Microchip Technology Inc. ...
Page 61
... NOP instruction). The PIC18F2455 and PIC18F4455 each have 24 Kbytes of Flash memory and can store up to 12,288 single-word instructions. The PIC18F2550 and PIC18F4550 each have 32 Kbytes of Flash memory and can store up to 16,384 single-word instructions ...
Page 62
... PIC18F2455/2550/4455/4550 5.1.1 PROGRAM COUNTER The Program Counter (PC) specifies the address of the instruction to fetch for execution. The bits wide and is contained in three separate 8-bit registers. The low byte, known as the PCL register, is both readable and writable. The high byte, or PCH register, contains the PC< ...
Page 63
... Note 1: Bit 7 and bit 6 are cleared by user software POR. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and sets the STKUNF bit, while the Stack Pointer remains at zero ...
Page 64
... PIC18F2455/2550/4455/4550 5.1.2.4 Stack Full and Underflow Resets Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit in Configuration Register 4L. When STVREN is set, a full or underflow condition will set the appropriate STKFUL or STKUNF bit and then cause a device Reset. When ...
Page 65
... All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 5.2.2 INSTRUCTION FLOW/PIPELINING An “ ...
Page 66
... PIC18F2455/2550/4455/4550 5.2.3 INSTRUCTIONS IN PROGRAM MEMORY The program memory is addressed in bytes. Instruc- tions are stored as two bytes or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSb = 0). To maintain alignment with instruction boundaries, the PC increments in steps of 2 and the LSb will always read ‘ ...
Page 67
... PIC18F2455/2550/4455/4550 devices implement eight complete banks, for a total of 2048 bytes. Figure 5-5 shows the data memory organization for the devices. The data memory contains Special Function Registers (SFRs) and General Purpose Registers (GPRs). The SFRs are used for control and status of the controller and peripheral functions, while GPRs are used for data storage and scratchpad operations in the user’ ...
Page 68
... PIC18F2455/2550/4455/4550 FIGURE 5-5: DATA MEMORY MAP BSR<3:0> 00h = 0000 Bank 0 FFh 00h = 0001 Bank 1 FFh 00h = 0010 Bank 2 FFh 00h = 0011 Bank 3 FFh 00h = 0100 Bank 4 FFh = 0101 00h Bank 5 FFh 00h = 0110 Bank 6 FFh 00h = 0111 Bank 7 FFh 00h = 1000 ...
Page 69
... Access RAM bit (the ‘a’ parameter in the instruction). When ‘a’ is equal to ‘1’, the instruction uses the BSR and the 8-bit address included in the opcode for the data memory address. When ‘a’ is ‘0’, © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Data Memory 000h 7 00h ...
Page 70
... PIC18F2455/2550/4455/4550 5.3.5 SPECIAL FUNCTION REGISTERS The Special Function Registers (SFRs) are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM in the data memory space. SFRs start at the top of data memory and extend down- ward to occupy the top segment of Bank 15, from F60h to FFFh ...
Page 71
... RE3 is only available as a port pin when the MCLRE Configuration bit is clear; otherwise, the bit reads as ‘0’. 6: RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> C™ Slave mode only. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Bit 4 Bit 3 Bit 2 — Top-of-Stack Upper Byte (TOS<20:16>) — SP4 ...
Page 72
... PIC18F2455/2550/4455/4550 TABLE 5-2: REGISTER FILE SUMMARY (CONTINUED) File Name Bit 7 Bit 6 Bit 5 OSCCON IDLEN IRCF2 IRCF1 HLVDCON VDIRMAG — IRVST WDTCON — — (2) RCON IPEN SBOREN TMR1H Timer1 Register High Byte TMR1L Timer1 Register Low Byte T1CON RD16 T1RUN T1CKPS1 TMR2 ...
Page 73
... RE3 is only available as a port pin when the MCLRE Configuration bit is clear; otherwise, the bit reads as ‘0’. 6: RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> C™ Slave mode only. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Bit 4 Bit 3 Bit 2 — FREE WRERR WREN ...
Page 74
... PIC18F2455/2550/4455/4550 TABLE 5-2: REGISTER FILE SUMMARY (CONTINUED) File Name Bit 7 Bit 6 Bit 5 UCFG UTEYE UOEMON UADDR — ADDR6 ADDR5 UCON — PPBRST SE0 USTAT — ENDP3 ENDP2 UEIE BTSEE — UEIR BTSEF — UIE — SOFIE STALLIE UIR — SOFIF STALLIF UFRMH — ...
Page 75
... For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 It is recommended that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions are used to alter the STATUS register because these instructions do not affect the bits in the STATUS register ...
Page 76
... PIC18F2455/2550/4455/4550 5.4 Data Addressing Modes Note: The execution of some instructions in the core PIC18 instruction set are changed when the PIC18 extended instruction set is enabled. See Section 5.6 “Data Memory and the Extended Instruction Set” for more information. While the program memory can be addressed in only one way – ...
Page 77
... ECCh will be added to that of the W register and stored back in ECCh. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 mapped in the SFR space but are not physically imple- mented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. A read from INDF1, for example, reads the data at the address indicated by FSR1H:FSR1L ...
Page 78
... PIC18F2455/2550/4455/4550 5.4.3.2 FSR Registers and POSTINC, POSTDEC, PREINC and PLUSW In addition to the INDF operand, each FSR register pair also has four additional indirect operands. Like INDF, these are “virtual” registers that cannot be indirectly read or written to. Accessing these registers actually accesses the associated FSR register pair, but also performs a specific action on it stored value. They are: • ...
Page 79
... This special addressing mode is known as Indexed Addressing with Literal Offset or Indexed Literal Offset mode. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 When using the extended instruction set, this addressing mode requires the following: • The use of the Access Bank is forced (‘a’ = 0); ...
Page 80
... PIC18F2455/2550/4455/4550 FIGURE 5-8: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF (Opcode: 0010 01da ffff ffff) When and f ≥ 60h: The instruction executes in Direct Forced mode. ‘f’ is inter- preted as a location in the Access RAM between 060h and 0FFh ...
Page 81
... BSR. F60h FFFh © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Remapping of the Access Bank applies only to opera- tions using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit is ‘1’) will continue to use Direct Addressing as before. Any indirect or ...
Page 82
... PIC18F2455/2550/4455/4550 NOTES: DS39632E-page 80 © 2009 Microchip Technology Inc. ...
Page 83
... TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 6.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes DD between the program memory space and the data RAM: • ...
Page 84
... PIC18F2455/2550/4455/4550 FIGURE 6-2: TABLE WRITE OPERATION (1) Table Pointer TBLPTRU TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer actually points to one of 32 holding registers, the address of which is determined by TBLPTRL<4:0>. The process for physically writing data to the program memory array is discussed in Section 6.5 “Writing to Flash Program Memory”. ...
Page 85
... RD bit cannot be set when EEPGD = 1 or CFGS = 1 Does not initiate an EEPROM read Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 R/W-0 R/W-x R/W-0 (1) FREE ...
Page 86
... PIC18F2455/2550/4455/4550 6.2.2 TABLE LATCH REGISTER (TABLAT) The Table Latch (TABLAT 8-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. 6.2.3 TABLE POINTER REGISTER (TBLPTR) The Table Pointer (TBLPTR) register addresses a byte within the program memory ...
Page 87
... MOVF TABLAT, W MOVF WORD_ODD © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words ...
Page 88
... PIC18F2455/2550/4455/4550 6.4 Erasing Flash Program Memory The minimum erase block is 32 words or 64 bytes. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be Bulk Erased. Word Erase in the Flash array is not supported. When initiating an erase sequence from the micro- controller itself, a block of 64 bytes of program memory is erased ...
Page 89
... CFGS bit to access program memory; • set WREN to enable byte writes. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 The long write is necessary for programming the internal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer ...
Page 90
... PIC18F2455/2550/4455/4550 EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY MOVLW D'64’ MOVWF COUNTER MOVLW BUFFER_ADDR_HIGH MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L MOVLW CODE_ADDR_UPPER MOVWF TBLPTRU MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL READ_BLOCK TBLRD*+ MOVF TABLAT, W MOVWF POSTINC0 DECFSZ COUNTER BRA ...
Page 91
... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. Note 1: Bit 21 of the TBLPTRU allows access to the device Configuration bits. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 ; point to Flash program memory ; access Flash program memory ; enable write to memory ...
Page 92
... PIC18F2455/2550/4455/4550 NOTES: DS39632E-page 90 © 2009 Microchip Technology Inc. ...
Page 93
... EEPROM memory. When clear, operations will access the data EEPROM memory. When set, program memory is accessed. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Control bit, CFGS, determines if the access will be to the Configuration registers or to program memory/data EEPROM memory. When set, subsequent operations access Configuration registers ...
Page 94
... PIC18F2455/2550/4455/4550 REGISTER 7-1: EECON1: DATA EEPROM CONTROL REGISTER 1 R/W-x R/W-x U-0 EEPGD CFGS — bit 7 Legend Settable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory ...
Page 95
... BSF INTCON, GIE BCF EECON1, WREN © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Additionally, the WREN bit in EECON1 must be set to enable writes. This mechanism prevents accidental writes to data EEPROM due to unexpected code exe- cution (i.e., runaway programs). The WREN bit should be kept clear at all times except when updating the EEPROM ...
Page 96
... PIC18F2455/2550/4455/4550 7.5 Operation During Code-Protect Data EEPROM memory has its own code-protect bits in Configuration Words. External read operations are disabled if code protection is enabled. The microcontroller itself can both read and write to the internal data EEPROM regardless of the state of the code-protect Configuration bit. Refer to Section 25.0 “ ...
Page 97
... CFGS IPR2 OSCFIP CMIP PIR2 OSCFIF CMIF PIE2 OSCFIE CMIE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Bit 5 Bit 4 Bit 3 Bit 2 TMR0IE INT0IE RBIE TMR0IF — FREE WRERR ...
Page 98
... PIC18F2455/2550/4455/4550 NOTES: DS39632E-page 96 © 2009 Microchip Technology Inc. ...
Page 99
... Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 EXAMPLE 8-1: MOVF ARG1, W MULWF ARG2 EXAMPLE 8-2: MOVF ARG1, W MULWF ARG2 BTFSC ARG2, SB ...
Page 100
... PIC18F2455/2550/4455/4550 Example 8-3 shows the sequence unsigned multiplication. Equation 8-1 shows the algorithm that is used. The 32-bit result is stored in four registers (RES3:RES0). EQUATION 8- UNSIGNED MULTIPLICATION ALGORITHM ARG1H:ARG1L • ARG2H:ARG2L RES3:RES0 = 16 (ARG1H • ARG2H • (ARG1H • ARG2L • (ARG1L • ARG2H • 2 (ARG1L • ...
Page 101
... INTCON<7> is the GIE bit which enables/disables all interrupt sources. All interrupts branch to address 000008h in Compatibility mode. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 When an interrupt is responded to, the global interrupt enable bit is cleared to disable further interrupts. If the devices have IPEN bit is cleared, this is the GIE bit ...
Page 102
... PIC18F2455/2550/4455/4550 FIGURE 9-1: INTERRUPT LOGIC Peripheral Interrupt Flag bit Peripheral Interrupt Enable bit Peripheral Interrupt Priority bit TMR1IF TMR1IE TMR1IP From USB USBIF Interrupt Logic USBIE USBIP Additional Peripheral Interrupts High-Priority Interrupt Generation Low-Priority Interrupt Generation Peripheral Interrupt Flag bit Peripheral Interrupt Enable bit ...
Page 103
... A mismatch condition will continue to set this bit. Reading PORTB, and then waiting one additional instruction cycle, will end the mismatch condition and allow the bit to be cleared. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Note: Interrupt flag bits are set when an interrupt ...
Page 104
... PIC18F2455/2550/4455/4550 REGISTER 9-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 R/W-1 RBPU INTEDG0 INTEDG1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values ...
Page 105
... Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 R/W-0 R/W-0 U-0 ...
Page 106
... PIC18F2455/2550/4455/4550 9.3 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Request (Flag) registers (PIR1 and PIR2). REGISTER 9-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 ...
Page 107
... No TMR1 or TMR3 register capture occurred Compare mode TMR1 or TMR3 register compare match occurred (must be cleared in software TMR1 or TMR3 register compare match occurred PWM mode: Unused in this mode. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 R/W-0 R/W-0 R/W-0 EEIF BCLIF HLVDIF U = Unimplemented bit, read as ‘0’ ...
Page 108
... PIC18F2455/2550/4455/4550 9.4 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of periph- eral interrupt sources, there are two Peripheral Interrupt Enable registers (PIE1 and PIE2). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts ...
Page 109
... Disabled bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 R/W-0 R/W-0 R/W-0 EEIE BCLIE HLVDIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 ...
Page 110
... PIC18F2455/2550/4455/4550 9.5 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Priority registers (IPR1 and IPR2). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set ...
Page 111
... TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 R/W-1 R/W-1 R/W-1 EEIP BCLIP HLVDIP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 112
... PIC18F2455/2550/4455/4550 9.6 RCON Register The RCON register contains flag bits which are used to determine the cause of the last Reset or wake-up from Idle or Sleep modes. RCON also contains the IPEN bit which enables interrupt priorities. REGISTER 9-10: RCON: RESET CONTROL REGISTER (1) R/W-0 ...
Page 113
... BSR_TEMP, BSR MOVF W_TEMP, W MOVFF STATUS_TEMP, STATUS © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 9.8 TMR0 Interrupt In 8-bit mode (which is the default), an overflow in the TMR0 register (FFh → 00h) will set flag bit, TMR0IF. In 16-bit mode, an overflow in the TMR0H:TMR0L regis- ter pair (FFFFh → 0000h) will set TMR0IF. The interrupt can be enabled/disabled by setting/clearing enable bit, TMR0IE (INTCON< ...
Page 114
... PIC18F2455/2550/4455/4550 NOTES: DS39632E-page 112 © 2009 Microchip Technology Inc. ...
Page 115
... PORTA pin an output (i.e., put the contents of the output latch on the selected pin). © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Reading the PORTA register reads the status of the pins; writing to it will write to the port latch. The Data Latch register (LATA) is also memory mapped ...
Page 116
... PIC18F2455/2550/4455/4550 TABLE 10-1: PORTA I/O SUMMARY TRIS Pin Function Setting RA0/AN0 RA0 0 1 AN0 1 RA1/AN1 RA1 0 1 AN1 1 RA2/AN2/ RA2 0 V -/CV REF REF 1 AN2 REF CV x REF RA3/AN3/ RA3 REF 1 AN3 REF RA4/T0CKI/ RA4 0 C1OUT/RCV 1 T0CKI 1 C1OUT 0 RCV x RA5/AN4/SS/ RA5 0 HLVDIN/C2OUT ...
Page 117
... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. Note 1: RA6 and its associated latch and data direction bits are enabled as I/O pins based on oscillator configuration; otherwise, they are read as ‘0’. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Bit 5 Bit 4 Bit 3 Bit 2 ...
Page 118
... PIC18F2455/2550/4455/4550 10.2 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bidirectional port. The corre- sponding Data Direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i ...
Page 119
... Alternate pin assignment for CCP2 when CCP2MX = 0. Default assignment is RC1. 3: All other pin functions are disabled when ICSP™ or ICD operation is enabled. 4: 40/44-pin devices only. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 I/O I/O Type DIG LATB<0> data output; not affected by analog input. IN TTL PORTB< ...
Page 120
... PIC18F2455/2550/4455/4550 TABLE 10-3: PORTB I/O SUMMARY (CONTINUED) TRIS Pin Function Setting RB6/KBI2/ RB6 OUT 0 PGC 1 KBI2 1 PGC x RB7/KBI3/ RB7 OUT 0 PGD 1 KBI3 1 PGD OUT x x Legend: OUT = Output Input, ANA = Analog Signal, DIG = Digital Output Schmitt Buffer Input C/SMB = I C/SMBus input buffer, TTL = TTL Buffer Input Don’t care (TRIS bit does not affect port direction or is ...
Page 121
... Additional information on configuring USB options is provided in Section 17.2.2.2 “External Transceiver”. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 When enabling peripheral functions on PORTC pins other than RC4 and RC5, care should be taken in defin- ing the TRIS bits. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input ...
Page 122
... PIC18F2455/2550/4455/4550 TABLE 10-5: PORTC I/O SUMMARY TRIS Pin Function Setting RC0/T1OSO/ RC0 0 T13CKI 1 T1OSO x T13CKI 1 RC1/T1OSI/ RC1 0 CCP2/UOE 1 T1OSI x (1) CCP2 0 1 UOE 0 RC2/CCP1/ RC2 0 P1A 1 CCP1 0 1 (3) P1A 0 (2) RC4/D-/VM RC4 — (2) D- — (2) — (2) VM — (2) RC5/D+/VP RC5 — ...
Page 123
... PPBRST Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTC. Note 1: RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0). © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 I/O I/O Type OUT DIG LATC<7> data output. ...
Page 124
... PIC18F2455/2550/4455/4550 10.4 PORTD, TRISD and LATD Registers Note: PORTD is only available on 40/44-pin devices. PORTD is an 8-bit wide, bidirectional port. The corre- sponding Data Direction register is TRISD. Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a high-impedance mode) ...
Page 125
... P1D 0 Legend: OUT = Output Input, DIG = Digital Output Schmitt Buffer Input, TTL = TTL Buffer Input Note 1: May be configured for tri-state during Enhanced PWM shutdown events. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 I/O I/O Type OUT DIG LATD<0> data output PORTD<0> data input. ...
Page 126
... PIC18F2455/2550/4455/4550 TABLE 10-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Name Bit 7 Bit 6 (3) PORTD RD7 RD6 (3) LATD LATD7 LATD6 (3) TRISD TRISD7 TRISD6 (3) PORTE RDPU — (3) (3) CCP1CON P1M1 P1M0 (3) SPPCON — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTD. ...
Page 127
... PORTE, TRISE and LATE Registers Depending on the particular PIC18F2455/2550/4455/ 4550 device selected, PORTE is implemented in two different ways. For 40/44-pin devices, PORTE is a 4-bit wide port. Three pins (RE0/AN5/CK1SPP, RE1/AN6/CK2SPP and RE2/AN7/OESPP) are individually configurable as inputs or outputs. These pins have Schmitt Trigger input buffers. When selected as an analog input, these pins will read as ‘ ...
Page 128
... PIC18F2455/2550/4455/4550 TABLE 10-9: PORTE I/O SUMMARY TRIS Pin Function Setting RE0/AN5/ RE0 0 CK1SPP 1 AN5 1 CK1SPP 0 RE1/AN6/ RE1 0 CK2SPP 1 AN6 1 CK2SPP 0 RE2/AN7/ RE2 0 OESPP 1 AN7 1 OESPP 0 (1) MCLR MCLR/V / — PP RE3 (1) V — PP (1) RE3 — Legend: OUT = Output Input, ANA = Analog Signal, DIG = Digital Output Schmitt Buffer Input Note 1: RE3 does not have a corresponding TRISE< ...
Page 129
... Prescale value 000 = 1:2 Prescale value © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 The T0CON register (Register 11-1) controls all aspects of the module’s operation, including the prescale selection both readable and writable. A simplified block diagram of the Timer0 module in 8-bit mode is shown in Figure 11-1 ...
Page 130
... PIC18F2455/2550/4455/4550 11.1 Timer0 Operation Timer0 can operate as either a timer or a counter; the mode is selected by clearing (T0CON<5>). In Timer mode, the module increments on every clock by default unless a different prescaler value is selected (see Section 11.3 “Prescaler”). If the TMR0 register is written to, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register ...
Page 131
... Legend: — = unimplemented locations, read as ‘0’. Shaded cells are not used by Timer0. Note 1: RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read ‘0’. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 11.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control and can be changed “ ...
Page 132
... PIC18F2455/2550/4455/4550 NOTES: DS39632E-page 130 © 2009 Microchip Technology Inc. ...
Page 133
... TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 A simplified block diagram of the Timer1 module is shown in Figure 12-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 12-2. The module incorporates its own low-power oscillator to provide an additional clocking option ...
Page 134
... PIC18F2455/2550/4455/4550 12.1 Timer1 Operation Timer1 can operate in one of these modes: • Timer • Synchronous Counter • Asynchronous Counter The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). When TMR1CS is cleared (= 0), Timer1 increments on every internal instruction FIGURE 12-1: TIMER1 BLOCK DIAGRAM ...
Page 135
... XTAL 32.768 kHz T1OSO Note: See the notes with Table 12-1 for additional information about capacitor selection. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 TABLE 12-1: CAPACITOR SELECTION FOR THE TIMER OSCILLATOR Osc Type Freq LP 32 kHz Note 1: Microchip suggests these values as a starting point in validating the oscillator circuit ...
Page 136
... PIC18F2455/2550/4455/4550 12.3.3 TIMER1 OSCILLATOR LAYOUT CONSIDERATIONS The Timer1 oscillator circuit draws very little power during operation. Due to the low-power nature of the oscillator, it may also be sensitive to rapidly changing signals in close proximity. The oscillator circuit, shown in Figure 12-3, should be located as close as possible to the microcontroller. ...
Page 137
... RETURN CLRF hours RETURN © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 following a later Timer1 increment. This can be done by monitoring TMR1L within the interrupt routine until it increments, and then updating the TMR1H:TMR1L reg- ister pair while the clock is low, or one-half of the period of the clock source. Assuming that Timer1 is being used as a Real-Time Clock, the clock source is a 32.768 kHz crystal oscillator ...
Page 138
... PIC18F2455/2550/4455/4550 TABLE 12-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Name Bit 7 Bit 6 INTCON GIE/GIEH PEIE/GIEL TMR0IE (1) PIR1 SPPIF ADIF (1) PIE1 SPPIE ADIE (1) IPR1 SPPIP ADIP TMR1L Timer1 Register Low Byte TMR1H TImer1 Register High Byte T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC Legend: — ...
Page 139
... Timer2 is off bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 13.1 Timer2 Operation In normal operation, TMR2 is incremented from 00h on each clock (F /4). A 2-bit counter/prescaler on the OSC clock input gives direct input, divide-by-4 and divide-by- 16 prescale options. These are selected by the prescaler control bits, T2CKPS1:T2CKPS0 (T2CON< ...
Page 140
... PIC18F2455/2550/4455/4550 13.2 Timer2 Interrupt Timer2 can also generate an optional device interrupt. The Timer2 output signal (TMR2 to PR2 match) pro- vides the input for the 4-bit output counter/postscaler. This counter generates the TMR2 match interrupt flag which is latched in TMR2IF (PIR1<1>). The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE (PIE1< ...
Page 141
... TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 A simplified block diagram of the Timer3 module is shown in Figure 14-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 14-2. The Timer3 module is controlled through the T3CON register (Register 14-1) ...
Page 142
... PIC18F2455/2550/4455/4550 14.1 Timer3 Operation Timer3 can operate in one of three modes: • Timer • Synchronous Counter • Asynchronous Counter The operating mode is determined by the clock select bit, TMR3CS (T3CON<1>). When TMR3CS is cleared (= 0), Timer3 increments on every internal instruction FIGURE 14-1: TIMER3 BLOCK DIAGRAM ...
Page 143
... RD16 T3CCP2 T3CKPS1 T3CKPS0 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 14.4 Timer3 Interrupt The TMR3 register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and overflows to 0000h. The Timer3 interrupt, if enabled, is generated on overflow and is latched in interrupt flag bit, TMR3IF (PIR2< ...
Page 144
... PIC18F2455/2550/4455/4550 NOTES: DS39632E-page 142 © 2009 Microchip Technology Inc. ...
Page 145
... CAPTURE/COMPARE/PWM (CCP) MODULES PIC18F2455/2550/4455/4550 devices all have two CCP (Capture/Compare/PWM) modules. Each module contains a 16-bit register, which can operate as a 16-bit Capture register, a 16-bit Compare register or a PWM Master/Slave Duty Cycle register. In 28-pin devices, the two standard CCP modules (CCP1 and CCP2) operate as described in this chapter ...
Page 146
... PIC18F2455/2550/4455/4550 15.1 CCP Module Configuration Each Capture/Compare/PWM module is associated with a control register (generically, CCPxCON) and a data register (CCPRx). The data register, in turn, is comprised of two 8-bit registers: CCPRxL (low byte) and CCPRxH (high byte). All registers are both readable and writable. 15.1.1 ...
Page 147
... Q1:Q4 CCP2CON<3:0> CCP2 pin Prescaler ÷ © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 15.2.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE interrupt enable bit clear to avoid false interrupts. The interrupt flag bit, CCPxIF, should also be cleared following any such change in operating mode ...
Page 148
... PIC18F2455/2550/4455/4550 15.3 Compare Mode In Compare mode, the 16-bit CCPRx register value is constantly compared against either the TMR1 or TMR3 register pair value. When a match occurs, the CCPx pin can be: • driven high • driven low • toggled (high-to-low or low-to-high) • remain unchanged (that is, reflects the state of the ...
Page 149
... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Capture/Compare, Timer1 or Timer3. Note 1: The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’. 2: These bits are unimplemented on 28-pin devices; always maintain these bits clear. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Bit 5 Bit 4 Bit 3 Bit 2 TMR0IE ...
Page 150
... PIC18F2455/2550/4455/4550 15.4 PWM Mode In Pulse-Width Modulation (PWM) mode, the CCPx pin produces 10-bit resolution PWM output. Since the CCP2 pin is multiplexed with a PORTB or PORTC data latch, the appropriate TRIS bit must be cleared to make the CCP2 pin an output. Note: Clearing the CCP2CON register will force ...
Page 151
... CCP1 in 28-pin devices. The operation of this feature is discussed in detail in Section 16.4.7 “Enhanced PWM Auto-Shutdown”. Auto-shutdown features are not available for CCP2. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 EQUATION 15-3: PWM Resolution (max) Note: If the PWM duty cycle value is longer than the PWM period, the CCPx pin will not be cleared ...
Page 152
... PIC18F2455/2550/4455/4550 TABLE 15-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2 Name Bit 7 Bit 6 INTCON GIE/GIEH PEIE/GIEL (1) RCON IPEN SBOREN (2) PIR1 SPPIF ADIF (2) PIE1 SPPIE ADIE (2) IPR1 SPPIP ADIP TRISB TRISB7 TRISB6 TRISC TRISC7 TRISC6 TMR2 Timer2 Register PR2 Timer2 Period Register T2CON — ...
Page 153
... PWM mode: P1A, P1C active-low; P1B, P1D active-high 1111 = PWM mode: P1A, P1C active-low; P1B, P1D active-low © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 automatic shutdown and restart. The Enhanced features are discussed in detail in Section 16.4 “Enhanced PWM Mode”. Capture, Compare and single output PWM functions of the ECCP module are the same as described for the standard CCP module ...
Page 154
... PIC18F2455/2550/4455/4550 In addition to the expanded range of modes available through the CCP1CON register, the ECCP module has two additional registers associated with Enhanced PWM operation and auto-shutdown features. They are: • ECCP1DEL (PWM Dead-Band Delay) • ECCP1AS (ECCP Auto-Shutdown Control) 16.1 ECCP Outputs and Configuration The Enhanced CCP module may have up to four PWM outputs, depending on the selected operating mode ...
Page 155
... PR2 Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock bits of the prescaler, to create the 10-bit time base. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 16.4.1 PWM PERIOD The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the ...
Page 156
... PIC18F2455/2550/4455/4550 16.4.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits 10-bit resolution is available. The CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The PWM duty cycle is calculated by the following equation ...
Page 157
... Prescale Value) OSC • Duty Cycle = T * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) OSC • Delay = (ECCP1DEL<6:0>) OSC Note 1: Dead-band delay is programmed using the ECCP1DEL register (Section 16.4.6 “Programmable Dead-Band Delay”). © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 0 Duty Cycle Period (1) Delay Delay 0 Duty ...
Page 158
... PIC18F2455/2550/4455/4550 16.4.4 HALF-BRIDGE MODE In the Half-Bridge Output mode, two pins are used as outputs to drive push-pull loads. The PWM output sig- nal is output on the P1A pin, while the complementary PWM output signal is output on the P1B pin (Figure 16-4). This mode can be used for half-bridge ...
Page 159
... Note 1: At this time, the TMR2 register is equal to the PR2 register. Note 2: Output signal is shown as active-high. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 P1A, P1B, P1C and P1D outputs are multiplexed with the PORTC<2>, PORTD<7> data latches. The TRISC<2>, TRISD<5>, TRISD<6> and TRISD<7> bits must be cleared to make the P1A, P1B, P1C and P1D pins outputs ...
Page 160
... PIC18F2455/2550/4455/4550 FIGURE 16-7: EXAMPLE OF FULL-BRIDGE APPLICATION PIC18FX455/X550 P1A P1B P1C P1D 16.4.5.1 Direction Change in Full-Bridge Mode In the Full-Bridge Output mode, the P1M1 bit in the CCP1CON register allows the user to control the forward/reverse direction. When the application firm- ware changes this direction control bit, the module will assume the new direction on the next PWM cycle ...
Page 161
... Note 1: All signals are shown as active-high the turn-on delay of power switch QC and its driver the turn-off delay of power switch QD and its driver. OFF © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 (1) Period DC (Note 2) , depending on the Timer2 prescaler value. The modulated P1B and P1D signals Forward Period t1 ...
Page 162
... PIC18F2455/2550/4455/4550 16.4.6 PROGRAMMABLE DEAD-BAND DELAY Note: Programmable dead-band delay is not implemented in 28-pin devices with standard CCP modules. In half-bridge applications where all power switches are modulated at the PWM frequency at all times, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are ...
Page 163
... PSSBD1:PSSBD0: Pins B and D Shutdown State Control bits 1x = Pins B and D tri-state 01 = Drive Pins B and D to ‘1’ Drive Pins B and D to ‘0’ Note 1: Reserved on 28-pin devices; maintain these bits clear. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 R/W-0 R/W-0 R/W-0 ECCPAS0 PSSAC1 PSSAC0 U = Unimplemented bit, read as ‘ ...
Page 164
... PIC18F2455/2550/4455/4550 16.4.7.1 Auto-Shutdown and Auto-Restart The auto-shutdown feature can be configured to allow automatic restarts of the module following a shutdown event. This is enabled by setting the PRSEN bit of the ECCP1DEL register (ECCP1DEL<7>). In Shutdown mode with PRSEN = 1 (Figure 16-10), the ECCPASE bit will remain set for as long as the cause of the shutdown continues ...
Page 165
... Enable the CCP1/P1A, P1B, P1C and/or P1D pin outputs by clearing the respective TRIS bits. • Clear the ECCPASE bit (ECCP1AS<7>). © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 16.4.10 OPERATION IN POWER-MANAGED MODES In Sleep mode, all clock sources are disabled. Timer2 will not increment and the state of the module will not change ...
Page 166
... PIC18F2455/2550/4455/4550 TABLE 16-3: REGISTERS ASSOCIATED WITH ECCP MODULE AND TIMER1 TO TIMER3 Name Bit 7 Bit 6 INTCON GIE/GIEH PEIE/GIEL (1) RCON IPEN SBOREN (2) IPR1 SPPIP ADIP (2) PIR1 SPPIF ADIF (2) PIE1 SPPIE ADIE IPR2 OSCFIP CMIP PIR2 OSCFIF CMIF PIE2 OSCFIE CMIE TRISB TRISB7 TRISB6 ...
Page 167
... The internal pull-up resistors should be disabled (UPUEN = 0) if external pull-up resistors are used not enable the internal regulator when using an external 3.3V supply. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 The SIE can be interfaced directly to the USB, utilizing the internal transceiver can be connected through an external transceiver ...
Page 168
... PIC18F2455/2550/4455/4550 17.2 USB Status and Control The operation of the USB module is configured and managed through three control registers. In addition, a total of 22 registers are used to manage the actual USB transactions. The registers are: • USB Control register (UCON) • USB Configuration register (UCFG) • ...
Page 169
... On-Chip Pull-up Resistor Enable • On-Chip Transceiver Enable • Ping-Pong Buffer Usage © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 The UCFG register also contains two bits which aid in module testing, debugging and USB certifications. These bits control output enable state monitoring and eye pattern generation ...
Page 170
... PIC18F2455/2550/4455/4550 REGISTER 17-2: UCFG: USB CONFIGURATION REGISTER R/W-0 R/W-0 U-0 (1) UTEYE UOEMON — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 UTEYE: USB Eye Pattern Test Enable bit 1 = Eye pattern test enabled 0 = Eye pattern test disabled ...
Page 171
... Note: The above setting shows a typical connection for a full-speed configuration using an on-chip regulator and an external pull-up resistor. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 17.2.2.5 Ping-Pong Buffer Configuration The usage of ping-pong buffers is configured using the PPB1:PPB0 bits. Refer to Section 17.4.4 “Ping-Pong Buffering” for a complete explanation of the ping-pong buffers ...
Page 172
... PIC18F2455/2550/4455/4550 17.2.2.8 Internal Regulator The PIC18FX455/X550 devices have a built-in 3.3V reg- ulator to provide power to the internal transceiver and provide a source for the internal/external pull-ups. An external 220 nF (±20%) capacitor is required for stability. Note: The drive from V is sufficient to only USB drive an external pull-up in addition to the internal transceiver ...
Page 173
... The last transaction was to the Odd BD bank 0 = The last transaction was to the Even BD bank bit 0 Unimplemented: Read as ‘0’ Note 1: This bit is only valid for endpoints with available Even and Odd BD registers. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 R-x R-x R-x ENDP1 ENDP0 DIR U = Unimplemented bit, read as ‘ ...
Page 174
... PIC18F2455/2550/4455/4550 17.2.4 USB ENDPOINT CONTROL Each of the 16 possible bidirectional endpoints has its own independent control register, UEPn (where ‘n’ rep- resents the endpoint number). Each register has an identical complement of control bits. The prototype is shown in Register 17-4. The EPHSHK bit (UEPn<4>) controls handshaking for the endpoint ...
Page 175
... SIE should not be accessed by the microcontroller. A semaphore mechanism is used to determine the access to a particular buffer at any given time. This is discussed in Section 17.4.1.1 “Buffer Ownership”. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 FIGURE 17-5: Banks Banks (USB RAM) ...
Page 176
... PIC18F2455/2550/4455/4550 17.4 Buffer Descriptors and the Buffer Descriptor Table The registers in Bank 4 are used specifically for end- point buffer control in a structure known as the Buffer Descriptor Table (BDT). This provides a flexible method for users to construct and control endpoint buffers of various lengths and configuration. ...
Page 177
... Either, with error x Legend don’t care © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 the SIE. When enabled, it checks the data packet’s par- ity against the value of DTS (BDnSTAT<6>). If a packet arrives with an incorrect synchronization, the data will essentially be ignored. It will not be written to the USB RAM and the USB transfer complete interrupt flag will not be set ...
Page 178
... PIC18F2455/2550/4455/4550 REGISTER 17-5: BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER (BD0STAT THROUGH BD63STAT), CPU MODE (DATA IS WRITTEN TO THE SIDE) R/W-x R/W-x R/W-x (1) (2) UOWN DTS KEN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set (1) bit 7 UOWN: USB Own bit ...
Page 179
... These bits are updated by the SIE to reflect the actual number of bytes received on an OUT transfer and the actual number of bytes transmitted transfer. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 The 10-bit byte count is distributed over two registers. The lower 8 bits of the count reside in the BDnCNT register. The upper two bits reside in BDnSTAT< ...
Page 180
... PIC18F2455/2550/4455/4550 17.4.4 PING-PONG BUFFERING An endpoint is defined to have a ping-pong buffer when it has two sets of BD entries: one set for an Even transfer and one set for an Odd transfer. This allows the CPU to process one BD while the SIE is processing the other BD. Double-buffering BDs in this way allows for maximum throughput to/from the USB ...
Page 181
... Prior to turning the buffer descriptor over to the SIE (UOWN bit is cleared), bits 5 through 2 of the BDnSTAT register are used to configure the KEN, INCDIS, DTSEN and BSTALL settings. 4: This bit is ignored unless DTSEN = 1. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 BDs Assigned to Endpoint Mode 1 Mode 2 (Ping-Pong on all EPs) ...
Page 182
... PIC18F2455/2550/4455/4550 17.5 USB Interrupts The USB module can generate multiple interrupt con- ditions. To accommodate all of these interrupt sources, the module is provided with its own interrupt logic structure, similar to that of the microcontroller. USB interrupts are enabled with one set of control registers and trapped with a separate set of flag registers. All sources are funneled into a single USB interrupt request, USBIF (PIR2< ...
Page 183
... Only error conditions enabled through the UEIE register will set this bit. This bit is a status bit only and cannot be set or cleared by the user. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 When the USB module is in the Low-Power Suspend mode (UCON<1> = 1), the SIE does not get clocked. ...
Page 184
... PIC18F2455/2550/4455/4550 17.5.1.1 Bus Activity Detect Interrupt Bit (ACTVIF) The ACTVIF bit cannot be cleared immediately after the USB module wakes up from Suspend or while the USB module is suspended. A few clock cycles are required to synchronize the internal hardware state machine before the ACTVIF bit can be cleared by firmware ...
Page 185
... URSTIE: USB Reset Interrupt Enable bit 1 = USB Reset interrupt enabled 0 = USB Reset interrupt disabled © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 The values in this register only affect the propagation of an interrupt condition to the microcontroller’s inter- rupt logic. The flag bits are still set by their interrupt conditions, allowing them to be polled and serviced without actually generating an interrupt ...
Page 186
... PIC18F2455/2550/4455/4550 17.5.3 USB ERROR INTERRUPT STATUS REGISTER (UEIR) The USB Error Interrupt Status register (Register 17-9) contains the flag bits for each of the error sources within the USB peripheral. Each of these sources is controlled by a corresponding interrupt enable bit in the UEIE register. All of the USB error flags are ORed together to generate the USB Error Interrupt Flag (UERRIF) at the top level of the interrupt logic ...
Page 187
... PID check failure interrupt enabled 0 = PID check failure interrupt disabled © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 As with the UIE register, the enable bits only affect the propagation of an interrupt condition to the micro- controller’s interrupt logic. The flag bits are still set by ...
Page 188
... PIC18F2455/2550/4455/4550 17.6 USB Power Modes Many USB applications will likely have several different sets of power requirements and configuration. The most common power modes encountered are Bus Power Only, Self-Power Only and Dual Power with Self-Power Dominance. The most common cases are presented here ...
Page 189
... This table includes only those hardware mapped SFRs located in Bank 15 of the data memory space. The Buffer Descriptor registers, which are mapped into Bank 4 and are not true SFRs, are listed separately in Table 17-5. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Refer to Section 18.0 “Streaming Parallel Port” for more information about the SPP. ...
Page 190
... PIC18F2455/2550/4455/4550 Name Bit 7 Bit 6 PIE2 OSCFIE CMIE USBIE UCON — PPBRST UCFG UTEYE UOEMON USTAT — ENDP3 ENDP2 UADDR — ADDR6 ADDR5 UFRML FRM7 FRM6 UFRMH — — UIR — SOFIF STALLIF UIE — SOFIE STALLIE UEIR BTSEF — UEIE BTSEE — ...
Page 191
... FIGURE 17-13: USB LAYERS Interface Endpoint Endpoint © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 17.10.3 TRANSFERS There are four transfer types defined in the USB specification. • Isochronous: This type provides a transfer method for large amounts of data (up to 1023 bytes) with timely delivery ensured; ...
Page 192
... PIC18F2455/2550/4455/4550 The USB specification limits the power taken from the bus. Each device is ensured 100 mA at approximately 5V (one unit load). Additional power may be requested maximum of 500 mA. Note that power above one unit load is a request and the host or hub is not obligated to provide the extra current. Thus, a device ...
Page 193
... SPPEN: SPP Enable bit 1 = SPP is enabled 0 = SPP is disabled © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 In addition, the SPP can provide time multiplexed addressing information along with the data by using the second strobe output. Thus, the USB endpoint number can be written in conjunction with the data for that endpoint ...
Page 194
... PIC18F2455/2550/4455/4550 REGISTER 18-2: SPPCFG: SPP CONFIGURATION REGISTER R/W-0 R/W-0 R/W-0 CLKCFG1 CLKCFG0 CSEN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-6 CLKCFG1:CLKCFG0: SPP Clock Configuration bits 1x = CLK1 toggles on read or write of an Odd endpoint address; CLK2 toggles on read or write of an Even endpoint address 01 = CLK1 toggles on write ...
Page 195
... TIMING FOR USB WRITE ADDRESS AND READ DATA (4 WAIT STATES) USB Clock OESPP CSSPP CK1SPP CK2SPP Write Address SPP<7:0> 2 Wait States © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 DATA Write Data Read Data MOVWF SPPDATA MOVF SPPDATA, W Write Data 2 Wait States 2 Wait States Read Data ...
Page 196
... PIC18F2455/2550/4455/4550 18.2 Setup for USB Control When the SPP is configured for USB operation, data can be clocked directly to and from the USB peripheral without intervention of the microcontroller; thus, no process time is required. Data is clocked into or out from the SPP with endpoint (address) information first, followed by one or more bytes of data, as shown in Figure 18-5 ...
Page 197
... Endpoint Address 0 © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 3. Read the data from the SPPDATA register; the data from the previous read operation is returned. The SPP automatically starts the read cycle for the next read. 4. Monitor the SPPBUSY bit to determine when the data has been read ...
Page 198
... PIC18F2455/2550/4455/4550 TABLE 18-1: REGISTERS ASSOCIATED WITH THE STREAMING PARALLEL PORT Name Bit 7 Bit 6 (3) SPPCON — — (3) SPPCFG CLKCFG1 CLKCFG0 (3) SPPEPS RDSPP WRSPP (3) SPPDATA DATA7 DATA6 (3) PIR1 SPPIF ADIF (3) PIE1 SPPIE ADIE (3) IPR1 SPPIP ADIP (3) PORTE RDPU — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for the Streaming Parallel Port. ...
Page 199
... SPI mode. Additional details are provided under the individual sections. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 19.3 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four modes of the SPI are supported. To accomplish communication, typically three pins are used: • ...
Page 200
... PIC18F2455/2550/4455/4550 19.3.1 REGISTERS The MSSP module has four registers for SPI mode operation. These are: • MSSP Control Register 1 (SSPCON1) • MSSP Status Register (SSPSTAT) • Serial Receive/Transmit Buffer Register (SSPBUF) • MSSP Shift Register (SSPSR) – Not directly accessible SSPCON1 and SSPSTAT are the control and status registers in SPI mode operation ...