PIC18F2455-I/SP Microchip Technology, PIC18F2455-I/SP Datasheet
PIC18F2455-I/SP
Specifications of PIC18F2455-I/SP
Available stocks
Related parts for PIC18F2455-I/SP
PIC18F2455-I/SP Summary of contents
Page 1
... Revision ID value appear in the Output window. Note: If you are unable to extract the silicon revision level, please contact your local Microchip sales office for assistance. The DEVREV values for the various PIC18F2455/2550/ 4455/4550 silicon revisions are shown in Table 1. Revision ID for Silicon Revision A3 B4 ...
Page 2
... PIC18F2455/2550/4455/4550 TABLE 2: SILICON ISSUE SUMMARY Item Module Feature Number Nine-Bit EUSART 1. mode Sixteen-Bit Timer1/3 2. mode Slave MSSP 3. Transmit Two-Cycle Interrupts 4. Instructions ECCPASE ECCP 5. Bit ECCP Auto-Restart 6. Special Event ECCP 7. Trigger ADC Offset Error 8. BOR V 9. BOR SIE IN USB 10. Endpoint RDPU PORTD 11 ...
Page 3
... EUSART Interrupts 41. Note 1: Only those issues indicated in the last column apply to the current silicon revision. © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Issue Summary Clearing SBOREN can cause BOR baud rate not meeting formula SPI slave not meeting timing parameter 70 Need delay between consecutive writes ...
Page 4
... PIC18F2455/2550/4455/4550 Silicon Errata Issues Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated by the shaded column in the following tables apply to the current silicon revision (B7). 1. Module: EUSART When performing back-to-back transmission in 9-bit mode (TX9D bit in the TXSTA register is set), an ongoing transmission’ ...
Page 5
... ISR code here : RETFIEFAST © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Assembly Language Programming Either of two work arounds can be used: • If any two-cycle instruction is used to modify the WREG, BSR or STATUS register, do not use the RETFIE FAST instruction to return from the interrupt ...
Page 6
... PIC18F2455/2550/4455/4550 C Programming Language The exact work around depends on the compiler in use. Please refer to your C compiler documentation for details. ® If using the Microchip MPLAB C18 C Compiler, define both high and low-priority interrupt handler functions as “low priority” by directive. pragma interruptlow directive instructs the compiler to not use the EXAMPLE 2: INTERRUPT WORK AROUND – ...
Page 7
... Affected Silicon Revisions © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 7. Module: ECCP When operating either Timer1 or Timer3 as a counter with a prescale value other than 1:1 and operating the ECCP in Compare mode with the Special CCP1M<3:0> = 1011), the Special Event Trigger Reset of the timer occurs as soon as there is a match CCPR1H:CCPR1L ...
Page 8
... The A/D offset is greater than the specified limit in Table 28-8 of the Device Data Sheet. The updated conditions and limits are shown in bold text in Table 28-8. Work around Any of three work arounds may be used. TABLE 28-8: A/D CONVERTER CHARACTERISTICS:PIC18F2455/2550/4455/4550 (INDUSTRIAL) PIC18LF2455/2550/4455/4550 (INDUSTRIAL) Param Symbol Characteristic No. A06A ...
Page 9
... Work around None. Affected Silicon Revisions © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 14. Module: USB The Ping-Pong Buffer mode in which the ping-pong buffers are enabled for Endpoints (UCFG (PPB<1:0) = 11) is not supported. Work around Use other Ping-Pong Buffer modes. Affected Silicon Revisions A3 ...
Page 10
... PIC18F2455/2550/4455/4550 17. Module: MSSP It has been observed that following a Power-on 2 Reset, the I C mode may not initialize properly by just configuring the SCL and SDA pins as either inputs or outputs. This has only been seen in a few unique system environments. A test of a statistically significant sample of pre- ...
Page 11
... Affected Silicon Revisions © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 20. Module: EUSART In 9-Bit Asynchronous Full-Duplex Receive mode, the received data may be corrupted if the TX9D bit (TXSTA<0>) is not modified immediately after the RCIDL bit (BAUDCON<6>) is set. Work around Write to TX9D only when a reception is not in progress (RCIDL = 1) ...
Page 12
... PIC18F2455/2550/4455/4550 22. Module: EUSART With the auto-wake-up option enabled by setting the WUE bit (BAUDCON<1>), (PIR1<5>) bit will become set on a high-to-low transition on the RX pin. However, the WUE bit may not clear within low-to-high CY transition on RX. While the WUE bit is set, reading the Receive Buf- fer (RCREG) will not clear the RCIF interrupt flag ...
Page 13
... C event to maintain normal operation. Affected Silicon Revisions © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 28. Module: EUSART /64 or The EUSART auto-baud feature may periodically OSC measure the incoming baud rate incorrectly. The rate of incorrect baud-rate measurements will depend on the frequency of the incoming synchronization byte and the system clock frequency ...
Page 14
... PIC18F2455/2550/4455/4550 31. Module: MSSP 2 When operated in I C™ Master mode, the I baud rate may be somewhat slower than predicted by the following formula Master mode, clock = --------------------------------------------- - • SSPADD Work around If the target application is sensitive to the baud rate and requires more precision, the SSPADD value can be adjusted to compensate ...
Page 15
... © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 35. Module: Resets (BOR) Certain operating conditions can move the effec- tive Brown-out Reset (BOR) threshold outside of the range specified in the electrical characteristics of the Device Data Sheet (parameter D005). The BOR threshold has been observed to increase with some table read operations ...
Page 16
... PIC18F2455/2550/4455/4550 38. Module: MSSP If the application firmware is expecting to receive valid data, in either SPI Slave or Master mode, the firmware must read from the SSPBUF register before writing the next byte to transmit to SSPBUF. If the firmware does not read from SSPBUF, the BF bit (SSPSTAT<0>) can still be set from the pre- vious transaction ...
Page 17
... Tcy delay nop ;1 Tcy delay (two total) ;CPU may now execute 2 cycle instructions © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 40. Module: MSSP (I When in I clock stretching, the first clock pulse after the slave releases the SCL line may be narrower than the configured clock width. This may result in the slave missing the first clock in the next transmission/ reception ...
Page 18
... PIC18F2455/2550/4455/4550 Data Sheet Clarifications The following typographic corrections and clarifications are to be noted for the latest version of the device data sheet (DS39632D): Note: Corrections are shown in bold. Where possible, the original bold text formatting has been removed for clarity. EXAMPLE 12-1: ...
Page 19
... V at all times, even with the USB regulator disabled.” © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 4. Module: Master Synchronous Serial Port In Section 19.3.5 “Master Mode,” the second paragraph of the second column is corrected to read, “This allows a maximum data rate (at 48 MHz) of 12.00 Mbps.” ...
Page 20
... RC3 and RC4. The following relevant portion of the table indicates the corrections. (For clarity, the corrected items appear in bold text – all other text appears in plain text for purposes of this errata.) 28.3 DC Characteristics: PIC18F2455/2550/4455/4550 (Industrial) PIC18LF2455/2550/4455/4550 (Industrial) (Partial Presentation) DC CHARACTERISTICS Param Symbol Characteristic No ...
Page 21
... TABLE 28-5: USB INTERNAL VOLTAGE REGULATOR SPECIFICATIONS (PARTIAL PRESENTATION) Operating Conditions: -40°C < T < +85°C (unless otherwise stated). A Param Sym Characteristics No. D323 V Regulator Output Voltage USBANA © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Min Typ Max Units 3.0 — 3.6 Comments ≥ 4. DS80478A-page 21 ...
Page 22
... PIC18F2455/2550/4455/4550 10. Module: MSSP (SPI Master) In Section 19.3.5, “Master Mode,” the following content is added: When used in Timer2 Output/2 mode, the SPI bit rate can be configured using the PR2 Period register and the Timer2 prescaler. To operate in this mode, firmware must first ini- tialize and enable the Timer2 module before it can be used with the MSSP ...
Page 23
... Revision B4 Silicon Errata” • DS80322, “PIC18F2455/2550/4455/4550 Revision B5 Silicon Errata” • DS80335, “PIC18F2455/2550/4455/4550 Revision B6 Silicon Errata” • DS80388, “PIC18F2455/2550/4455/4550 Revision B7 Silicon Errata” • DS80278, “PIC18F2455/2550/4455/4550 Data Sheet Errata” © 2009 Microchip Technology Inc. PIC18F2455/2550/4455/4550 C Master) and DS80478A-page 23 ...
Page 24
... PIC18F2455/2550/4455/4550 NOTES: DS80478A-page 24 © 2009 Microchip Technology Inc. ...
Page 25
... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
Page 26
... Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2009 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...