PIC18F2455-I/SP Microchip Technology, PIC18F2455-I/SP Datasheet
PIC18F2455-I/SP
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PIC18F2455-I/SP Summary of contents
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... PIC18F2455/2550/4455/4550 28/40/44-Pin, High Performance, Enhanced Flash, USB Microcontrollers © 2007 Microchip Technology Inc. Data Sheet with nanoWatt Technology DS39632D ...
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... Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... PIC18F4550 32K 16384 2048 © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Peripheral Highlights: • High-Current Sink/Source: 25 mA/25 mA • Three External Interrupts • Four Timer modules (Timer0 to Timer3) • Capture/Compare/PWM (CCP) modules: - Capture is 16-bit, max. resolution 5 Compare is 16-bit, max. resolution 83 PWM output: PWM resolution 10-bit • ...
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... PIC18F2455/2550/4455/4550 Pin Diagrams 28-Pin PDIP, SOIC MCLR/V /RE3 PP RA0/AN0 RA1/AN1 RA2/AN2/V -/CV REF RA3/AN3/V REF RA4/T0CKI/C1OUT/RCV RA5/AN4/SS/HLVDIN/C2OUT V OSC1/CLKI OSC2/CLKO/RA6 RC0/T1OSO/T13CKI (1) RC1/T1OSI/CCP2 /UOE RC2/CCP1 V 40-Pin PDIP MCLR/V /RE3 PP RA0/AN0 RA1/AN1 RA2/AN2/V -/CV REF RA3/AN3/V REF RA4/T0CKI/C1OUT/RCV RA5/AN4/SS/HLVDIN/C2OUT RE0/AN5/CK1SPP RE1/AN6/CK2SPP RE2/AN7/OESPP V V OSC1/CLKI OSC2/CLKO/RA6 RC0/T1OSO/T13CKI ...
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... RC7/RX/DT/SDO RB0/AN12/INT0/FLT0/SDI/SDA RB1/AN10/INT1/SCK/SCL RB2/AN8/INT2/VMO Note 1: RB3 is the alternate pin for CCP2 multiplexing. 2: Special ICPORTS features available in select circumstances. See Section 25.9 “Special ICPORT Features (Designated Packages Only)” for more information. © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 33 NC/ICRST 1 32 RC0/T1OSO/T13CKI 2 OSC2/CLKO/RA6 31 3 ...
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... Appendix E: Migration From Mid-Range to Enhanced Devices ......................................................................................................... 411 Appendix F: Migration From High-End to Enhanced Devices............................................................................................................ 411 Index .................................................................................................................................................................................................. 413 The Microchip Web Site ..................................................................................................................................................................... 425 Customer Change Notification Service .............................................................................................................................................. 425 Customer Support .............................................................................................................................................................................. 425 Reader Response .............................................................................................................................................................................. 426 PIC18F2455/2550/4455/4550 Product Identification System ............................................................................................................ 427 DS39632D-page 4 Preliminary © 2007 Microchip Technology Inc. ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Preliminary DS39632D-page 5 ...
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... PIC18F2455/2550/4455/4550 NOTES: DS39632D-page 6 Preliminary © 2007 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC18F2455/2550/4455/4550 1.1.3 MULTIPLE OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC18F2455/2550/4455/4550 family offer twelve different oscillator options, allowing users a wide range of choices in developing application hardware. These include: • Four Crystal modes using crystals or ceramic resonators. ...
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... DS39632D-page 8 1.3 Details on Individual Family Members Devices in the PIC18F2455/2550/4455/4550 family are available in 28-pin and 40/44-pin packages. Block diagrams for the two groups are shown in Figure 1-1 and Figure 1-2. The devices are differentiated from each other in six ways: 1 ...
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... Stack Underflow (PWRT, OST), MCLR (optional), Programmable Low-Voltage Detect Programmable Brown-out Reset Instruction Set 75 Instructions; 83 with Extended Instruction Set Packages © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 PIC18F2455 PIC18F2550 DC – 48 MHz DC – 48 MHz 24576 32768 12288 16384 2048 2048 256 256 19 19 ...
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... PIC18F2455/2550/4455/4550 FIGURE 1-1: PIC18F2455/2550 (28-PIN) BLOCK DIAGRAM Table Pointer<21> 8 inc/dec logic PCLATU PCLATH 21 20 PCU PCH PCL Program Counter 31 Level Stack Address Latch Program Memory STKPTR (24/32 Kbytes) Data Latch 8 Table Latch ROM Latch Instruction Bus <16> IR Instruction State Machine Decode & ...
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... These pins are only available on 44-pin TQFP packages under certain conditions. Refer to Section 25.9 “Special ICPORT Features (Designated Packages Only)” for additional information. 4: RB3 is the alternate pin for CCP2 multiplexing. © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Data Bus<8> Data Latch 8 Data Memory ...
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... PIC18F2455/2550/4455/4550 TABLE 1-2: PIC18F2455/2550 PINOUT I/O DESCRIPTIONS Pin Number Pin Name Type PDIP, SOIC MCLR/V /RE3 1 PP MCLR V PP RE3 OSC1/CLKI 9 OSC1 CLKI OSC2/CLKO/RA6 10 OSC2 CLKO RA6 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared. ...
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... TABLE 1-2: PIC18F2455/2550 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Type PDIP, SOIC RA0/AN0 2 RA0 AN0 RA1/AN1 3 RA1 AN1 RA2/AN2/V -/CV 4 REF REF RA2 AN2 V - REF CV REF RA3/AN3 REF RA3 AN3 V + REF RA4/T0CKI/C1OUT/RCV 6 RA4 T0CKI C1OUT RCV RA5/AN4/SS/ 7 HLVDIN/C2OUT RA5 ...
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... PIC18F2455/2550/4455/4550 TABLE 1-2: PIC18F2455/2550 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Type PDIP, SOIC RB0/AN12/INT0/FLT0/ 21 SDI/SDA RB0 AN12 INT0 FLT0 SDI SDA RB1/AN10/INT1/SCK/ 22 SCL RB1 AN10 INT1 SCK SCL RB2/AN8/INT2/VMO 23 RB2 AN8 INT2 VMO RB3/AN9/CCP2/VPO 24 RB3 AN9 (1) CCP2 VPO RB4/AN11/KBI0 ...
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... TABLE 1-2: PIC18F2455/2550 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Type PDIP, SOIC RC0/T1OSO/T13CKI 11 RC0 T1OSO T13CKI RC1/T1OSI/CCP2/UOE 12 RC1 T1OSI (2) CCP2 UOE RC2/CCP1 13 RC2 CCP1 RC4/D-/VM 15 RC4 D- VM RC5/D+/VP 16 RC5 D+ VP RC6/TX/CK 17 RC6 TX CK RC7/RX/DT/SDO 18 RC7 RX DT SDO RE3 — ...
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... PIC18F2455/2550/4455/4550 TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS Pin Number Pin Name PDIP QFN TQFP MCLR/V /RE3 MCLR V PP RE3 OSC1/CLKI 13 32 OSC1 CLKI OSC2/CLKO/RA6 14 33 OSC2 CLKO RA6 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared ...
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... Default assignment for CCP2 when CCP2MX Configuration bit is set. 3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No Connect unless ICPRT is set and the DEBUG Configuration bit is cleared. © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Pin Buffer Type Type PORTA is a bidirectional I/O port ...
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... PIC18F2455/2550/4455/4550 TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP QFN TQFP RB0/AN12/INT0 FLT0/SDI/SDA RB0 AN12 INT0 FLT0 SDI SDA RB1/AN10/INT1/SCK SCL RB1 AN10 INT1 SCK SCL RB2/AN8/INT2/VMO 35 11 RB2 AN8 INT2 VMO RB3/AN9/CCP2/VPO 36 12 RB3 AN9 (1) CCP2 ...
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... Default assignment for CCP2 when CCP2MX Configuration bit is set. 3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No Connect unless ICPRT is set and the DEBUG Configuration bit is cleared. © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Pin Buffer Type Type PORTC is a bidirectional I/O port ...
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... PIC18F2455/2550/4455/4550 TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP QFN TQFP RD0/SPP0 19 38 RD0 SPP0 RD1/SPP1 20 39 RD1 SPP1 RD2/SPP2 21 40 RD2 SPP2 RD3/SPP3 22 41 RD3 SPP3 RD4/SPP4 27 2 RD4 SPP4 RD5/SPP5/P1B 28 3 RD5 SPP5 P1B RD6/SPP6/P1C ...
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... Default assignment for CCP2 when CCP2MX Configuration bit is set. 3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No Connect unless ICPRT is set and the DEBUG Configuration bit is cleared. © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Pin Buffer Type Type PORTE is a bidirectional I/O port ...
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... PIC18F2455/2550/4455/4550 NOTES: DS39632D-page 22 Preliminary © 2007 Microchip Technology Inc. ...
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... They are discussed later in this chapter. 2.1.1 OSCILLATOR CONTROL The operation of the oscillator in PIC18F2455/2550/ 4455/4550 devices is controlled through two Configu- ration registers and two control registers. Configuration registers, CONFIG1L and CONFIG1H, select the oscillator mode and USB prescaler/postscaler options. ...
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... PIC18F2455/2550/4455/4550 FIGURE 2-1: PIC18F2455/2550/4455/4550 CLOCK DIAGRAM Primary Oscillator OSC2 Sleep OSC1 XT, HS, EC, ECIO Secondary Oscillator T1OSO T1OSCEN Enable Oscillator T1OSI OSCCON<6:4> Internal Oscillator Block 8 MHz Source 8 MHz (INTOSC) INTRC Source 31 kHz (INTRC) DS39632D-page 24 PIC18F2455/2550/4455/4550 PLLDIV ÷ 12 111 ÷ 10 110 USBDIV ÷ 6 ...
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... See the notes following Table 2-2 for additional information. Resonators Used: 4.0 MHz 8.0 MHz 16.0 MHz © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 TABLE 2-2: Osc Type XT HS Capacitor values are for design guidance only. These capacitors were tested with the crystals listed below for basic start-up and operation ...
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... XT and HS modes is also available in EC and ECIO modes. DS39632D-page 26 2.2.4 PLL FREQUENCY MULTIPLIER PIC18F2455/2550/4255/4550 devices include a Phase Locked Loop (PLL) circuit. This is provided specifically for USB applications with lower speed oscillators and can also be used as a microcontroller clock source. The PLL is enabled in HSPLL, XTPLL, ECPLL and ECPIO Oscillator modes ...
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... INTERNAL OSCILLATOR BLOCK The PIC18F2455/2550/4455/4550 devices include an internal oscillator block which generates two different clock signals; either can be used as the microcontroller’s clock source. If the USB peripheral is not used, the internal oscillator may eliminate the need for external oscillator circuits on the OSC1 and/or OSC2 pins. ...
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... PIC18F2455/2550/4455/4550 REGISTER 2-1: OSCTUNE: OSCILLATOR TUNING REGISTER R/W-0 U-0 U-0 INTSRC — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit 1 = 31.25 kHz device clock derived from 8 MHz INTOSC source (divide-by-256 enabled) ...
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... USB clock of 6 MHz). Note 1: Only valid when the USBDIV Configuration bit is cleared. © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 active and the controller clock source is one of the primary oscillator modes (XT EC, with or without the PLL). This restriction does not apply if the microcontroller clock source is the secondary oscillator or internal oscillator block ...
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... PIC18F2455/2550/4455/4550 TABLE 2-3: OSCILLATOR CONFIGURATION OPTIONS FOR USB OPERATION (CONTINUED) Input Oscillator PLL Division Frequency (PLLDIV2:PLLDIV0) ÷5 (100) 20 MHz ÷4 (011) 16 MHz ÷3 (010) 12 MHz ÷2 (001) 8 MHz ÷1 (000) 4 MHz Legend: All clock frequencies, except 24 MHz, are exclusively associated with full-speed USB operation (USB clock of 48 MHz). ...
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... Switching Like previous PIC18 enhanced PIC18F2455/2550/4455/4550 family includes a feature that allows the device clock source to be switched from the main oscillator to an alternate low-frequency clock source. PIC18F2455/2550/4455/4550 devices offer two alternate clock sources. When an alternate clock source is enabled, the various power-managed operating modes are available ...
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... PIC18F2455/2550/4455/4550 2.4.2 OSCILLATOR TRANSITIONS PIC18F2455/2550/4455/4550 devices contain circuitry to prevent clock “glitches” when switching between clock sources. A short pause in the device clock occurs during the clock switch. The length of this pause is the REGISTER 2-2: OSCCON: OSCILLATOR CONTROL REGISTER R/W-0 R/W-1 R/W-0 ...
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... Note: See Table 4-2 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset. © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 command over the USB. Once the module has sus- pended operation and shifted to a low-power state, the microcontroller may be safely put into Sleep mode. ...
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... PIC18F2455/2550/4455/4550 NOTES: DS39632D-page 34 Preliminary © 2007 Microchip Technology Inc. ...
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... POWER-MANAGED MODES PIC18F2455/2550/4455/4550 devices offer a total of seven operating modes for more efficient power management. These modes provide a variety of options for selective power conservation in applications where resources may be limited (i.e., battery-powered devices). There are three categories of power-managed modes: • Run modes • ...
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... PIC18F2455/2550/4455/4550 3.1.3 CLOCK TRANSITIONS AND STATUS INDICATORS The length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Three bits indicate the current clock source and its status. They are: • ...
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... PRI_RUN and RC_RUN modes during execution. However, a clock switch delay will occur during entry to and exit from RC_RUN mode. Therefore, if the primary clock source is the internal oscillator block, the use of RC_RUN mode is not recommended. © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 n-1 n (1) ...
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... PIC18F2455/2550/4455/4550 If the IRCF bits and the INTSRC bit are all clear, the INTOSC output is not enabled and the IOFS bit will remain clear; there will be no indication of the current clock source. The INTRC source is providing the device clocks. If the IRCF bits are changed from all clear (thus, ...
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... Sleep Mode The power-managed Sleep mode PIC18F2455/2550/4455/4550 devices is identical to the legacy Sleep mode offered in all other PIC devices entered by clearing the IDLEN bit (the default state on device Reset) and executing the SLEEP instruction. This shuts down the selected oscillator (Figure 3-5). All clock source status bits are cleared ...
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... PIC18F2455/2550/4455/4550 3.4.1 PRI_IDLE MODE This mode is unique among the three low-power Idle modes in that it does not disable the primary device clock. For timing sensitive applications, this allows for the fastest resumption of device operation, with its more accurate primary clock source, since the clock source does not have to “ ...
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... INTCON or PIE registers. The exit sequence is initiated when the corresponding interrupt flag bit is set. © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 On all exits from Idle or Sleep modes by interrupt, code execution branches to the interrupt vector if the GIE/GIEH bit (INTCON<7>) is set. Otherwise, code execution continues or resumes without branching (see Section 9.0 “ ...
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... PIC18F2455/2550/4455/4550 3.5.4 EXIT WITHOUT AN OSCILLATOR START-UP DELAY Certain exits from power-managed modes do not invoke the OST at all. There are two cases: • PRI_IDLE mode, where the primary clock source is not stopped; and • the primary clock source is not any of the modes ...
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... RESET The PIC18F2455/2550/4455/4550 devices differentiate between various kinds of Reset: a) Power-on Reset (POR) b) MCLR Reset during normal operation c) MCLR Reset during power-managed modes d) Watchdog Timer (WDT) Reset (during execution) e) Programmable Brown-out Reset (BOR) f) RESET Instruction g) Stack Full Reset h) Stack Underflow Reset ...
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... PIC18F2455/2550/4455/4550 REGISTER 4-1: RCON: RESET CONTROL REGISTER (1) R/W-0 R/W-1 U-0 IPEN SBOREN — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) ...
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... MCLR Reset path which detects and ignores small pulses. The MCLR pin is not driven low by any internal Resets, including the WDT. In PIC18F2455/2550/4455/4550 devices, the MCLR input can be disabled with the MCLRE Configuration bit. When MCLR is disabled, the pin becomes a digital input. See Section 10.5 “PORTE, TRISE and LATE Registers” ...
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... PIC18F2455/2550/4455/4550 4.4 Brown-out Reset (BOR) PIC18F2455/2550/4455/4550 devices implement a BOR circuit that provides the user with a number of configuration and power-saving options. The BOR is controlled by the BORV1:BORV0 BOREN1:BOREN0 Configuration bits. There are a total of four BOR configurations which are summarized in Table 4-1. The BOR threshold is set by the BORV1:BORV0 bits. If BOR is enabled (any values of BOREN1:BOREN0 except ‘ ...
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... Oscillator Start-up Timer (OST) • PLL Lock Time-out 4.5.1 POWER-UP TIMER (PWRT) The Power-up Timer (PWRT) of the PIC18F2455/2550/ 4455/4550 devices is an 11-bit counter which uses the INTRC source as the clock input. This yields an approximate time interval of 2048 x 32 μs = 65.6 ms. ...
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... PIC18F2455/2550/4455/4550 FIGURE 4-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 4-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO V ...
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... TIME-OUT SEQUENCE ON POR w/PLL ENABLED (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note 1024 clock cycles. OST ≈ max. First three stages of the Power-up Timer. T PLL © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 , V RISE > PWRT T OST T PWRT T OST T ...
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... PIC18F2455/2550/4455/4550 4.6 Reset State of Registers Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a “Reset state” depending on the type of Reset that occurred. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal oper- ation ...
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... See Table 4-3 for Reset value for specific condition. 5: PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 MCLR Resets, Power-on Reset, WDT Reset, Brown-out Reset ...
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... PIC18F2455/2550/4455/4550 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices INDF2 2455 2550 4455 4550 POSTINC2 2455 2550 4455 4550 POSTDEC2 2455 2550 4455 4550 PREINC2 2455 2550 4455 4550 PLUSW2 2455 2550 4455 4550 FSR2H 2455 2550 4455 4550 ...
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... See Table 4-3 for Reset value for specific condition. 5: PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 MCLR Resets, Power-on Reset, WDT Reset, Brown-out Reset ...
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... PIC18F2455/2550/4455/4550 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices IPR2 2455 2550 4455 4550 PIR2 2455 2550 4455 4550 PIE2 2455 2550 4455 4550 IPR1 2455 2550 4455 4550 2455 2550 4455 4550 PIR1 2455 2550 4455 4550 ...
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... See Table 4-3 for Reset value for specific condition. 5: PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 MCLR Resets, Power-on Reset, WDT Reset, Brown-out Reset ...
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... PIC18F2455/2550/4455/4550 NOTES: DS39632D-page 56 Preliminary © 2007 Microchip Technology Inc. ...
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... Additional detailed information on the operation of the Flash program memory is provided in Section 6.0 “Flash Program Memory”. Data EEPROM is discussed separately in Section 7.0 “Data EEPROM Memory”. FIGURE 5-1: PROGRAM MEMORY MAP AND STACK FOR PIC18F2455/2550/4455/4550 DEVICES PIC18FX455 PC<20:0> CALL, RCALL, RETURN, 21 RETFIE, RETLW, CALLW, ...
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... PIC18F2455/2550/4455/4550 5.1.1 PROGRAM COUNTER The Program Counter (PC) specifies the address of the instruction to fetch for execution. The bits wide and is contained in three separate 8-bit registers. The low byte, known as the PCL register, is both readable and writable. The high byte, or PCH register, contains the PC< ...
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... Note 1: Bit 7 and bit 6 are cleared by user software POR. © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and sets the STKUNF bit, while the Stack Pointer remains at zero ...
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... PIC18F2455/2550/4455/4550 5.1.2.4 Stack Full and Underflow Resets Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit in Configuration Register 4L. When STVREN is set, a full or underflow condition will set the appropriate STKFUL or STKUNF bit and then cause a device Reset. When ...
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... All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 5.2.2 INSTRUCTION FLOW/PIPELINING An “ ...
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... PIC18F2455/2550/4455/4550 5.2.3 INSTRUCTIONS IN PROGRAM MEMORY The program memory is addressed in bytes. Instruc- tions are stored as two bytes or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSb = 0). To maintain alignment with instruction boundaries, the PC increments in steps of 2 and the LSb will always read ‘ ...
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... PIC18F2455/2550/4455/4550 devices implement eight complete banks, for a total of 2048 bytes. Figure 5-5 shows the data memory organization for the devices. The data memory contains Special Function Registers (SFRs) and General Purpose Registers (GPRs). The SFRs are used for control and status of the controller and peripheral functions, while GPRs are used for data storage and scratchpad operations in the user’ ...
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... PIC18F2455/2550/4455/4550 FIGURE 5-5: DATA MEMORY MAP FOR PIC18F2455/2550/4455/4550 DEVICES BSR<3:0> 00h = 0000 Bank 0 FFh 00h = 0001 Bank 1 FFh 00h = 0010 Bank 2 FFh 00h = 0011 Bank 3 FFh 00h = 0100 Bank 4 FFh = 0101 00h Bank 5 FFh 00h = 0110 Bank 6 FFh 00h = 0111 Bank 7 ...
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... Access RAM bit (the ‘a’ parameter in the instruction). When ‘a’ is equal to ‘1’, the instruction uses the BSR and the 8-bit address included in the opcode for the data memory address. When ‘a’ is ‘0’, © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Data Memory 000h 7 00h ...
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... FFFh. A list of these registers is given in Table 5-1 and Table 5-2. The SFRs can be classified into two sets: those associated with the “core” device functionality (ALU, Resets and interrupts) and those related to the TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F2455/2550/4455/4550 DEVICES Address Name Address Name FFFh ...
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... TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2455/2550/4455/4550) File Name Bit 7 Bit 6 Bit 5 TOSU — — TOSH Top-of-Stack High Byte (TOS<15:8>) TOSL Top-of-Stack Low Byte (TOS<7:0>) STKPTR STKFUL STKUNF PCLATU — — PCLATH Holding Register for PC<15:8> PCL PC Low Byte (PC<7:0>) TBLPTRU — ...
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... PIC18F2455/2550/4455/4550 TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2455/2550/4455/4550) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 OSCCON IDLEN IRCF2 IRCF1 HLVDCON VDIRMAG — IRVST WDTCON — — (2) RCON IPEN SBOREN TMR1H Timer1 Register High Byte TMR1L Timer1 Register Low Byte T1CON RD16 T1RUN T1CKPS1 ...
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... TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2455/2550/4455/4550) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 EEADR EEPROM Address Register EEDATA EEPROM Data Register EECON2 EEPROM Control Register 2 (not a physical register) EECON1 EEPGD CFGS IPR2 OSCFIP CMIP USBIP PIR2 OSCFIF CMIF USBIF PIE2 OSCFIE CMIE ...
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... PIC18F2455/2550/4455/4550 TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2455/2550/4455/4550) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 UCFG UTEYE UOEMON UADDR — ADDR6 ADDR5 UCON — PPBRST SE0 USTAT — ENDP3 ENDP2 UEIE BTSEE — UEIR BTSEF — UIE — SOFIE STALLIE UIR — SOFIF ...
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... For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register. © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 It is recommended that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions are used to alter the STATUS register because these instructions do not affect the bits in the STATUS register ...
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... PIC18F2455/2550/4455/4550 5.4 Data Addressing Modes Note: The execution of some instructions in the core PIC18 instruction set are changed when the PIC18 extended instruction set is enabled. See Section 5.6 “Data Memory and the Extended Instruction Set” for more information. While the program memory can be addressed in only one way – ...
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... ECCh will be added to that of the W register and stored back in ECCh. © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 mapped in the SFR space but are not physically imple- mented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. A read from INDF1, for example, reads the data at the address indicated by FSR1H:FSR1L ...
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... PIC18F2455/2550/4455/4550 5.4.3.2 FSR Registers and POSTINC, POSTDEC, PREINC and PLUSW In addition to the INDF operand, each FSR register pair also has four additional indirect operands. Like INDF, these are “virtual” registers that cannot be indirectly read or written to. Accessing these registers actually accesses the associated FSR register pair, but also performs a specific action on it stored value. They are: • ...
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... This special addressing mode is known as Indexed Addressing with Literal Offset or Indexed Literal Offset mode. © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 When using the extended instruction set, this addressing mode requires the following: • The use of the Access Bank is forced (‘a’ = 0); ...
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... PIC18F2455/2550/4455/4550 FIGURE 5-8: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF (Opcode: 0010 01da ffff ffff) When and f ≥ 60h: The instruction executes in Direct Forced mode. ‘f’ is inter- preted as a location in the Access RAM between 060h and 0FFh ...
Page 79
... BSR. F60h FFFh © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Remapping of the Access Bank applies only to opera- tions using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit is ‘1’) will continue to use Direct Addressing as before. Any indirect or ...
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... PIC18F2455/2550/4455/4550 NOTES: DS39632D-page 78 Preliminary © 2007 Microchip Technology Inc. ...
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... TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 6.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes DD between the program memory space and the data RAM: • ...
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... PIC18F2455/2550/4455/4550 FIGURE 6-2: TABLE WRITE OPERATION (1) Table Pointer TBLPTRU TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer actually points to one of 32 holding registers, the address of which is determined by TBLPTRL<4:0>. The process for physically writing data to the program memory array is discussed in Section 6.5 “Writing to Flash Program Memory”. ...
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... RD bit cannot be set when EEPGD = 1 or CFGS = 1 Does not initiate an EEPROM read Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 R/W-0 R/W-x R/W-0 (1) FREE ...
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... PIC18F2455/2550/4455/4550 6.2.2 TABLE LATCH REGISTER (TABLAT) The Table Latch (TABLAT 8-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. 6.2.3 TABLE POINTER REGISTER (TBLPTR) The Table Pointer (TBLPTR) register addresses a byte within the program memory ...
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... MOVF TABLAT, W MOVF WORD_ODD © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words ...
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... PIC18F2455/2550/4455/4550 6.4 Erasing Flash Program Memory The minimum erase block is 32 words or 64 bytes. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be Bulk Erased. Word Erase in the Flash array is not supported. When initiating an erase sequence from the micro- controller itself, a block of 64 bytes of program memory is erased ...
Page 87
... CFGS bit to access program memory; • set WREN to enable byte writes. © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 The long write is necessary for programming the internal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer ...
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... PIC18F2455/2550/4455/4550 EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY MOVLW D'64’ MOVWF COUNTER MOVLW BUFFER_ADDR_HIGH MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L MOVLW CODE_ADDR_UPPER MOVWF TBLPTRU MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL READ_BLOCK TBLRD*+ MOVF TABLAT, W MOVWF POSTINC0 DECFSZ COUNTER BRA ...
Page 89
... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. Note 1: Bit 21 of the TBLPTRU allows access to the device Configuration bits. © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 ; point to Flash program memory ; access Flash program memory ; enable write to memory ...
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... PIC18F2455/2550/4455/4550 NOTES: DS39632D-page 88 Preliminary © 2007 Microchip Technology Inc. ...
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... EEPROM memory. When clear, operations will access the data EEPROM memory. When set, program memory is accessed. © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Control bit, CFGS, determines if the access will be to the Configuration registers or to program memory/data EEPROM memory. When set, subsequent operations access Configuration registers ...
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... PIC18F2455/2550/4455/4550 REGISTER 7-1: EECON1: DATA EEPROM CONTROL REGISTER 1 R/W-x R/W-x U-0 EEPGD CFGS — bit 7 Legend Settable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory ...
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... BSF INTCON, GIE BCF EECON1, WREN © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Additionally, the WREN bit in EECON1 must be set to enable writes. This mechanism prevents accidental writes to data EEPROM due to unexpected code exe- cution (i.e., runaway programs). The WREN bit should be kept clear at all times except when updating the EEPROM ...
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... PIC18F2455/2550/4455/4550 7.5 Operation During Code-Protect Data EEPROM memory has its own code-protect bits in Configuration Words. External read operations are disabled if code protection is enabled. The microcontroller itself can both read and write to the internal data EEPROM regardless of the state of the code-protect Configuration bit. Refer to Section 25.0 “ ...
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... CFGS IPR2 OSCFIP CMIP PIR2 OSCFIF CMIF PIE2 OSCFIE CMIE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Bit 5 Bit 4 Bit 3 Bit 2 TMR0IE INT0IE RBIE TMR0IF — FREE WRERR ...
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... PIC18F2455/2550/4455/4550 NOTES: DS39632D-page 94 Preliminary © 2007 Microchip Technology Inc. ...
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... Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 EXAMPLE 8-1: MOVF ARG1, W MULWF ARG2 EXAMPLE 8-2: MOVF ARG1, W MULWF ARG2 BTFSC ARG2, SB ...
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... PIC18F2455/2550/4455/4550 Example 8-3 shows the sequence unsigned multiplication. Equation 8-1 shows the algorithm that is used. The 32-bit result is stored in four registers (RES3:RES0). EQUATION 8- UNSIGNED MULTIPLICATION ALGORITHM ARG1H:ARG1L • ARG2H:ARG2L RES3:RES0 = (ARG1H • ARG2H • (ARG1H • ARG2L • (ARG1L • ARG2H • (ARG1L • ...
Page 99
... INTCON<7> is the GIE bit which enables/disables all interrupt sources. All interrupts branch to address 000008h in Compatibility mode. © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 When an interrupt is responded to, the global interrupt enable bit is cleared to disable further interrupts. If the devices have IPEN bit is cleared, this is the GIE bit ...
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... PIC18F2455/2550/4455/4550 FIGURE 9-1: INTERRUPT LOGIC Peripheral Interrupt Flag bit Peripheral Interrupt Enable bit Peripheral Interrupt Priority bit TMR1IF TMR1IE TMR1IP From USB USBIF Interrupt Logic USBIE USBIP Additional Peripheral Interrupts High Priority Interrupt Generation Low Priority Interrupt Generation Peripheral Interrupt Flag bit ...
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... Note 1: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit ...
Page 102
... PIC18F2455/2550/4455/4550 REGISTER 9-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 R/W-1 RBPU INTEDG0 INTEDG1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values ...
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... Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 R/W-0 R/W-0 U-0 ...
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... PIC18F2455/2550/4455/4550 9.3 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Request (Flag) registers (PIR1 and PIR2). REGISTER 9-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 ...
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... No TMR1 or TMR3 register capture occurred Compare mode TMR1 or TMR3 register compare match occurred (must be cleared in software TMR1 or TMR3 register compare match occurred PWM mode: Unused in this mode. © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 R/W-0 R/W-0 R/W-0 EEIF BCLIF HLVDIF U = Unimplemented bit, read as ‘0’ ...
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... PIC18F2455/2550/4455/4550 9.4 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of periph- eral interrupt sources, there are two Peripheral Interrupt Enable registers (PIE1 and PIE2). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts ...
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... Disabled bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 R/W-0 R/W-0 R/W-0 EEIE BCLIE HLVDIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 ...
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... PIC18F2455/2550/4455/4550 9.5 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Priority registers (IPR1 and IPR2). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set ...
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... TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 R/W-1 R/W-1 R/W-1 EEIP BCLIP HLVDIP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
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... PIC18F2455/2550/4455/4550 9.6 RCON Register The RCON register contains flag bits which are used to determine the cause of the last Reset or wake-up from Idle or Sleep modes. RCON also contains the IPEN bit which enables interrupt priorities. REGISTER 9-10: RCON: RESET CONTROL REGISTER (1) R/W-0 ...
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... BSR_TEMP, BSR MOVF W_TEMP, W MOVFF STATUS_TEMP, STATUS © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 9.8 TMR0 Interrupt In 8-bit mode (which is the default), an overflow in the TMR0 register (FFh → 00h) will set flag bit, TMR0IF. In 16-bit mode, an overflow in the TMR0H:TMR0L regis- ter pair (FFFFh → 0000h) will set TMR0IF. The interrupt can be enabled/disabled by setting/clearing enable bit, TMR0IE (INTCON< ...
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... PIC18F2455/2550/4455/4550 NOTES: DS39632D-page 110 Preliminary © 2007 Microchip Technology Inc. ...
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... PORTA pin an output (i.e., put the contents of the output latch on the selected pin). © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Reading the PORTA register reads the status of the pins; writing to it will write to the port latch. The Data Latch register (LATA) is also memory mapped ...
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... PIC18F2455/2550/4455/4550 TABLE 10-1: PORTA I/O SUMMARY TRIS Pin Function Setting RA0/AN0 RA0 0 1 AN0 1 RA1/AN1 RA1 0 1 AN1 1 RA2/AN2/ RA2 0 V -/CV REF REF 1 AN2 REF CV REF x RA3/AN3/ RA3 REF 1 AN3 REF 1 RA4/T0CKI/ RA4 0 C1OUT/RCV 1 T0CKI 1 C1OUT 0 RCV x RA5/AN4/SS/ RA5 0 HLVDIN/C2OUT 1 AN4 ...
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... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. Note 1: RA6 and its associated latch and data direction bits are enabled as I/O pins based on oscillator configuration; otherwise, they are read as ‘0’. © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Bit 5 Bit 4 Bit 3 Bit 2 ...
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... PIC18F2455/2550/4455/4550 10.2 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bidirectional port. The corre- sponding data direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i ...
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... Alternate pin assignment for CCP2 when CCP2MX = 0. Default assignment is RC1. 3: All other pin functions are disabled when ICSP™ or ICD operation is enabled. 4: 40/44-pin devices only. © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 I/O I/O Type DIG LATB<0> data output; not affected by analog input. IN TTL PORTB< ...
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... PIC18F2455/2550/4455/4550 TABLE 10-3: PORTB I/O SUMMARY (CONTINUED) TRIS Pin Function Setting RB6/KBI2/ RB6 OUT 0 PGC 1 KBI2 1 PGC x RB7/KBI3/ RB7 OUT 0 PGD 1 KBI3 1 PGD OUT x x Legend: OUT = Output Input, ANA = Analog Signal, DIG = Digital Output Schmitt Buffer Input C/SMB = I C/SMBus input buffer, TTL = TTL Buffer Input Don’t care (TRIS bit does not affect port direction or is ...
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... Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., put the contents of the output latch on the selected pin). In PIC18F2455/2550/4455/4550 devices, the RC3 pin is not implemented. The Data Latch register (LATC) is also memory mapped. Read-modify-write operations on the LATC register read and write the latched output value for PORTC ...
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... PIC18F2455/2550/4455/4550 TABLE 10-5: PORTC I/O SUMMARY TRIS Pin Function Setting RC0/T1OSO/ RC0 0 T13CKI 1 T1OSO x T13CKI 1 RC1/T1OSI/ RC1 0 CCP2/UOE 1 T1OSI x (1) CCP2 0 1 UOE 0 RC2/CCP1/ RC2 0 P1A 1 CCP1 0 1 (3) P1A 0 (2) RC4/D-/VM RC4 — (2) D- — (2) — (2) VM — (2) RC5/D+/VP RC5 — ...
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... PPBRST Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTC. Note 1: RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0). © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 I/O I/O Type OUT DIG LATC<7> data output. ...
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... PIC18F2455/2550/4455/4550 10.4 PORTD, TRISD and LATD Registers Note: PORTD is only available on 40/44-pin devices. PORTD is an 8-bit wide, bidirectional port. The corre- sponding data direction register is TRISD. Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a high-impedance mode) ...
Page 123
... P1D 0 Legend: OUT = Output Input, DIG = Digital Output Schmitt Buffer Input, TTL = TTL Buffer Input Note 1: May be configured for tri-state during Enhanced PWM shutdown events. © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 I/O I/O Type OUT DIG LATD<0> data output PORTD<0> data input. ...
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... PIC18F2455/2550/4455/4550 TABLE 10-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Name Bit 7 Bit 6 (3) PORTD RD7 RD6 (3) LATD LATD7 LATD6 (3) TRISD TRISD7 TRISD6 (3) PORTE RDPU — (3) (3) CCP1CON P1M1 P1M0 (3) SPPCON — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTD. ...
Page 125
... PORTE, TRISE and LATE Registers Depending on the particular PIC18F2455/2550/4455/ 4550 device selected, PORTE is implemented in two different ways. For 40/44-pin devices, PORTE is a 4-bit wide port. Three pins (RE0/AN5/CK1SPP, RE1/AN6/CK2SPP and RE2/AN7/OESPP) are individually configurable as inputs or outputs. These pins have Schmitt Trigger input buffers. When selected as an analog input, these pins will read as ‘ ...
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... PIC18F2455/2550/4455/4550 TABLE 10-9: PORTE I/O SUMMARY TRIS Pin Function Setting RE0/AN5/ RE0 0 CK1SPP 1 AN5 1 CK1SPP 0 RE1/AN6/ RE1 0 CK2SPP 1 AN6 1 CK2SPP 0 RE2/AN7/ RE2 0 OESPP 1 AN7 1 OESPP 0 (1) MCLR MCLR/V / — PP RE3 (1) V — PP (1) RE3 — Legend: OUT = Output Input, ANA = Analog Signal, DIG = Digital Output Schmitt Buffer Input Note 1: RE3 does not have a corresponding TRISE< ...
Page 127
... Prescale value 000 = 1:2 Prescale value © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 The T0CON register (Register 11-1) controls all aspects of the module’s operation, including the prescale selection both readable and writable. A simplified block diagram of the Timer0 module in 8-bit mode is shown in Figure 11-1 ...
Page 128
... PIC18F2455/2550/4455/4550 11.1 Timer0 Operation Timer0 can operate as either a timer or a counter; the mode is selected by clearing (T0CON<5>). In Timer mode, the module increments on every clock by default unless a different prescaler value is selected (see Section 11.3 “Prescaler”). If the TMR0 register is written to, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register ...
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... Legend: — = unimplemented locations, read as ‘0’. Shaded cells are not used by Timer0. Note 1: RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read ‘0’. © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 11.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control and can be changed “ ...
Page 130
... PIC18F2455/2550/4455/4550 NOTES: DS39632D-page 128 Preliminary © 2007 Microchip Technology Inc. ...
Page 131
... TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 A simplified block diagram of the Timer1 module is shown in Figure 12-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 12-2. The module incorporates its own low-power oscillator to provide an additional clocking option ...
Page 132
... PIC18F2455/2550/4455/4550 12.1 Timer1 Operation Timer1 can operate in one of these modes: • Timer • Synchronous Counter • Asynchronous Counter The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). When TMR1CS is cleared (= 0), Timer1 increments on every internal instruction FIGURE 12-1: TIMER1 BLOCK DIAGRAM ...
Page 133
... XTAL 32.768 kHz T1OSO Note: See the Notes with Table 12-1 for additional information about capacitor selection. © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 TABLE 12-1: CAPACITOR SELECTION FOR THE TIMER OSCILLATOR Osc Type Freq LP 32 kHz Note 1: Microchip suggests these values as a starting point in validating the oscillator circuit ...
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... PIC18F2455/2550/4455/4550 12.3.3 TIMER1 OSCILLATOR LAYOUT CONSIDERATIONS The Timer1 oscillator circuit draws very little power during operation. Due to the low-power nature of the oscillator, it may also be sensitive to rapidly changing signals in close proximity. The oscillator circuit, shown in Figure 12-3, should be located as close as possible to the microcontroller. ...
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... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. Note 1: These bits are unimplemented on 28-pin devices; always maintain these bits clear. © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 ; Preload TMR1 register pair ; for 1 second overflow ; Configure for external clock, ...
Page 136
... PIC18F2455/2550/4455/4550 NOTES: DS39632D-page 134 Preliminary © 2007 Microchip Technology Inc. ...
Page 137
... Timer2 is off bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 13.1 Timer2 Operation In normal operation, TMR2 is incremented from 00h on each clock (F /4). A 2-bit counter/prescaler on the OSC clock input gives direct input, divide-by-4 and divide-by- 16 prescale options. These are selected by the prescaler control bits, T2CKPS1:T2CKPS0 (T2CON< ...
Page 138
... PIC18F2455/2550/4455/4550 13.2 Timer2 Interrupt Timer2 also can generate an optional device interrupt. The Timer2 output signal (TMR2 to PR2 match) pro- vides the input for the 4-bit output counter/postscaler. This counter generates the TMR2 match interrupt flag which is latched in TMR2IF (PIR1<1>). The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE (PIE1< ...
Page 139
... TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 A simplified block diagram of the Timer3 module is shown in Figure 14-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 14-2. The Timer3 module is controlled through the T3CON register (Register 14-1) ...
Page 140
... PIC18F2455/2550/4455/4550 14.1 Timer3 Operation Timer3 can operate in one of three modes: • Timer • Synchronous Counter • Asynchronous Counter The operating mode is determined by the clock select bit, TMR3CS (T3CON<1>). When TMR3CS is cleared (= 0), Timer3 increments on every internal instruction FIGURE 14-1: TIMER3 BLOCK DIAGRAM ...
Page 141
... RD16 T3CCP2 T3CKPS1 T3CKPS0 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module. © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 14.4 Timer3 Interrupt The TMR3 register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and overflows to 0000h. The Timer3 interrupt, if enabled, is generated on overflow and is latched in interrupt flag bit, TMR3IF (PIR2< ...
Page 142
... PIC18F2455/2550/4455/4550 NOTES: DS39632D-page 140 Preliminary © 2007 Microchip Technology Inc. ...
Page 143
... CAPTURE/COMPARE/PWM (CCP) MODULES PIC18F2455/2550/4455/4550 devices all have two CCP (Capture/Compare/PWM) modules. Each module contains a 16-bit register, which can operate as a 16-bit Capture register, a 16-bit Compare register or a PWM Master/Slave Duty Cycle register. In 28-pin devices, the two standard CCP modules (CCP1 and CCP2) operate as described in this chapter ...
Page 144
... PIC18F2455/2550/4455/4550 15.1 CCP Module Configuration Each Capture/Compare/PWM module is associated with a control register (generically, CCPxCON) and a data register (CCPRx). The data register, in turn, is comprised of two 8-bit registers: CCPRxL (low byte) and CCPRxH (high byte). All registers are both readable and writable. 15.1.1 ...
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... Q1:Q4 CCP2CON<3:0> CCP2 pin Prescaler ÷ © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 15.2.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE interrupt enable bit clear to avoid false interrupts. The interrupt flag bit, CCPxIF, should also be cleared following any such change in operating mode ...
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... PIC18F2455/2550/4455/4550 15.3 Compare Mode In Compare mode, the 16-bit CCPRx register value is constantly compared against either the TMR1 or TMR3 register pair value. When a match occurs, the CCPx pin can be: • driven high • driven low • toggled (high-to-low or low-to-high) • remain unchanged (that is, reflects the state of the ...
Page 147
... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Capture/Compare, Timer1 or Timer3. Note 1: The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’. 2: These bits are unimplemented on 28-pin devices; always maintain these bits clear. © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Bit 5 Bit 4 Bit 3 Bit 2 TMR0IE ...
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... PIC18F2455/2550/4455/4550 15.4 PWM Mode In Pulse-Width Modulation (PWM) mode, the CCPx pin produces 10-bit resolution PWM output. Since the CCP2 pin is multiplexed with a PORTB or PORTC data latch, the appropriate TRIS bit must be cleared to make the CCP2 pin an output. Note: Clearing the CCP2CON register will force ...
Page 149
... CCP1 in 28-pin devices. The operation of this feature is discussed in detail in Section 16.4.7 “Enhanced PWM Auto-Shutdown”. Auto-shutdown features are not available for CCP2. © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 EQUATION 15-3: PWM Resolution (max) Note: If the PWM duty cycle value is longer than the PWM period, the CCPx pin will not be cleared ...
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... PIC18F2455/2550/4455/4550 TABLE 15-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2 Name Bit 7 Bit 6 INTCON GIE/GIEH PEIE/GIEL (1) RCON IPEN SBOREN (2) PIR1 SPPIF ADIF (2) PIE1 SPPIE ADIE (2) IPR1 SPPIP ADIP TRISB TRISB7 TRISB6 TRISC TRISC7 TRISC6 TMR2 Timer2 Register PR2 Timer2 Period Register T2CON — ...
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... PWM mode: P1A, P1C active-low; P1B, P1D active-high 1111 = PWM mode: P1A, P1C active-low; P1B, P1D active-low © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Enhanced features are discussed in detail in Section 16.4 “Enhanced PWM Mode”. Capture, Compare and single output PWM functions of the ECCP module are the same as described for the standard CCP module ...
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... PIC18F2455/2550/4455/4550 In addition to the expanded range of modes available through the CCP1CON register, the ECCP module has two additional registers associated with Enhanced PWM operation and auto-shutdown features. They are: • ECCP1DEL (Dead-Band Delay) • ECCP1AS (Auto-Shutdown Configuration) 16.1 ECCP Outputs and Configuration The Enhanced CCP module may have up to four PWM outputs, depending on the selected operating mode ...
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... PR2 Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock bits of the prescaler, to create the 10-bit time base. © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 16.4.1 PWM PERIOD The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the ...
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... PIC18F2455/2550/4455/4550 16.4.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits 10-bit resolution is available. The CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The PWM duty cycle is calculated by the following equation ...
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... Prescale Value) OSC • Duty Cycle = T * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) OSC • Delay = (ECCP1DEL<6:0>) OSC Note 1: Dead-band delay is programmed using the ECCP1DEL register (Section 16.4.6 “Programmable Dead-Band Delay”). © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 0 Duty Cycle Period (1) Delay Delay 0 Duty ...
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... PIC18F2455/2550/4455/4550 16.4.4 HALF-BRIDGE MODE In the Half-Bridge Output mode, two pins are used as outputs to drive push-pull loads. The PWM output sig- nal is output on the P1A pin, while the complementary PWM output signal is output on the P1B pin (Figure 16-4). This mode can be used for half-bridge ...
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... Note 1: At this time, the TMR2 register is equal to the PR2 register. Note 2: Output signal is shown as active-high. © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 P1A, P1B, P1C and P1D outputs are multiplexed with the PORTC<2>, PORTD<7> data latches. The TRISC<2>, TRISD<5>, TRISD<6> and TRISD<7> bits must be cleared to make the P1A, P1B, P1C and P1D pins outputs ...
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... PIC18F2455/2550/4455/4550 FIGURE 16-7: EXAMPLE OF FULL-BRIDGE APPLICATION PIC18FX455/X550 P1A P1B P1C P1D 16.4.5.1 Direction Change in Full-Bridge Mode In the Full-Bridge Output mode, the P1M1 bit in the CCP1CON register allows the user to control the forward/reverse direction. When the application firm- ware changes this direction control bit, the module will assume the new direction on the next PWM cycle ...
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... Note 1: All signals are shown as active-high the turn-on delay of power switch QC and its driver the turn-off delay of power switch QD and its driver. OFF © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 (1) Period DC (Note 2) , depending on the Timer2 prescaler value. The modulated P1B and P1D signals Forward Period t1 ...
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... PIC18F2455/2550/4455/4550 16.4.6 PROGRAMMABLE DEAD-BAND DELAY Note: Programmable dead-band delay is not implemented in 28-pin devices with standard CCP modules. In half-bridge applications where all power switches are modulated at the PWM frequency at all times, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are ...
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... PSSBD1:PSSBD0: Pins B and D Shutdown State Control bits 1x = Pins B and D tri-state 01 = Drive Pins B and D to ‘1’ Drive Pins B and D to ‘0’ Note 1: Reserved on 28-pin devices; maintain these bits clear. © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 R/W-0 R/W-0 R/W-0 ECCPAS0 PSSAC1 PSSAC0 U = Unimplemented bit, read as ‘ ...
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... PIC18F2455/2550/4455/4550 16.4.7.1 Auto-Shutdown and Auto-Restart The auto-shutdown feature can be configured to allow automatic restarts of the module following a shutdown event. This is enabled by setting the PRSEN bit of the ECCP1DEL register (ECCP1DEL<7>). In Shutdown mode with PRSEN = 1 (Figure 16-10), the ECCPASE bit will remain set for as long as the cause of the shutdown continues ...
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... Enable the CCP1/P1A, P1B, P1C and/or P1D pin outputs by clearing the respective TRIS bits. • Clear the ECCPASE bit (ECCP1AS<7>). © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 16.4.10 OPERATION IN POWER-MANAGED MODES In Sleep mode, all clock sources are disabled. Timer2 will not increment and the state of the module will not change ...
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... PIC18F2455/2550/4455/4550 TABLE 16-3: REGISTERS ASSOCIATED WITH ECCP MODULE AND TIMER1 TO TIMER3 Name Bit 7 Bit 6 INTCON GIE/GIEH PEIE/GIEL (1) RCON IPEN SBOREN (2) IPR1 SPPIP ADIP (2) PIR1 SPPIF ADIF (2) PIE1 SPPIE ADIE IPR2 OSCFIP CMIP PIR2 OSCFIF CMIF PIE2 OSCFIE CMIE TRISB TRISB7 TRISB6 ...
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... The internal pull-up resistors should be disabled (UPUEN = 0) if external pull-up resistors are used not enable the internal regulator when using an external 3.3V supply. © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 The SIE can be interfaced directly to the USB, utilizing the internal transceiver can be connected through an external transceiver ...
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... PIC18F2455/2550/4455/4550 17.2 USB Status and Control The operation of the USB module is configured and managed through three control registers. In addition, a total of 22 registers are used to manage the actual USB transactions. The registers are: • USB Control register (UCON) • USB Configuration register (UCFG) • ...
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... On-Chip Pull-up Resistor Enable • On-Chip Transceiver Enable • Ping-Pong Buffer Usage © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 The UCFG register also contains two bits which aid in module testing, debugging and USB certifications. These bits control output enable state monitoring and eye pattern generation ...
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... PIC18F2455/2550/4455/4550 REGISTER 17-2: UCFG: USB CONFIGURATION REGISTER R/W-0 R/W-0 U-0 (1) UTEYE UOEMON — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 UTEYE: USB Eye Pattern Test Enable bit 1 = Eye pattern test enabled 0 = Eye pattern test disabled ...
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... Note: The above setting shows a typical connection for a full-speed configuration using an on-chip regulator and an external pull-up resistor. © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 17.2.2.5 Ping-Pong Buffer Configuration The usage of ping-pong buffers is configured using the PPB1:PPB0 bits. Refer to Section 17.4.4 “Ping-Pong Buffering” for a complete explanation of the ping-pong buffers ...
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... PIC18F2455/2550/4455/4550 17.2.3 USB STATUS REGISTER (USTAT) The USB Status register reports the transaction status within the SIE. When the SIE issues a USB transfer complete interrupt, USTAT should be read to determine the status of the transfer. USTAT contains the transfer endpoint number, direction and Ping-Pong Buffer Pointer value (if used) ...
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... EPSTALL: Endpoint Stall Enable bit 1 = Endpoint n is stalled 0 = Endpoint n is not stalled Note 1: Valid only if Endpoint n is enabled; otherwise, the bit is ignored. © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 transactions. For Endpoint 0, this bit should always be cleared since the Endpoint 0 as the default control endpoint. ...
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... PIC18F2455/2550/4455/4550 17.2.5 USB ADDRESS REGISTER (UADDR) The USB Address register contains the unique USB address that the peripheral will decode when active. UADDR is reset to 00h when a USB Reset is received, indicated by URSTIF, or when a Reset is received from the microcontroller. The USB address must be written ...
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... Buffer descriptors not only define the size of an end- point buffer, but also determine its configuration and control. Most of the configuration is done with the BD Status register, BDnSTAT. Each BD has its own unique and correspondingly numbered BDnSTAT register. © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 FIGURE 17-6: Address 400h 401h Buffer ...
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... PIC18F2455/2550/4455/4550 The BDnSTAT byte of the BDT should always be the last byte updated when preparing to arm an endpoint. The SIE will clear the UOWN bit when a transaction has completed. The only exception to this is when KEN is enabled and/or BSTALL is enabled. No hardware mechanism exists to block access when the UOWN bit is set ...
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... OUT token. Together with BC<7:0>, the valid byte counts are 0-1023. Note 1: This bit must be initialized by the user to the desired value prior to enabling the USB module. 2: This bit is ignored unless DTSEN = 1. © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 R/W-x R/W-x INCDIS DTSEN U = Unimplemented bit, read as ‘0’ ...
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... PIC18F2455/2550/4455/4550 17.4.1.3 BDnSTAT Register (SIE Mode) When the BD and its buffer are owned by the SIE, most of the bits in BDnSTAT take on a different meaning. The configuration is shown in Register 17-6. Once UOWN is set, any data or control settings previously written there by the user will be overwritten with data from the SIE ...
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... BD32) Note: Memory area not shown to scale. © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 the completion of a transaction (UOWN cleared by the SIE), the pointer is toggled to the Odd BD. After the completion of the next transaction, the pointer is toggled back to the Even BD and so on. ...
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... PIC18F2455/2550/4455/4550 TABLE 17-4: ASSIGNMENT OF BUFFER DESCRIPTORS FOR THE DIFFERENT BUFFERING MODES Mode 0 Endpoint (No Ping-Pong) (Ping-Pong on EP0 OUT) Out In Out (E Legend: (E) = Even transaction buffer, (O) = Odd transaction buffer TABLE 17-5: SUMMARY OF USB BUFFER DESCRIPTOR TABLE REGISTERS Name Bit 7 Bit 6 (1) (4) BDnSTAT UOWN ...
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... The control transfer shown here is only an example showing events that can occur for every transaction. Typical control transfers will spread across multiple frames. © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Figure 17-8 shows the interrupt logic for the USB module. There are two layers of interrupt registers in the USB module. The top level consists of overall USB status interrupts ...
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... PIC18F2455/2550/4455/4550 17.5.1 USB INTERRUPT STATUS REGISTER (UIR) The USB Interrupt Status register (Register 17-7) con- tains the flag bits for each of the USB status interrupt sources. Each of these sources has a corresponding interrupt enable bit in the UIE register. All of the USB status flags are ORed together to generate the USBIF interrupt flag for the microcontroller’ ...
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... C: UCONbits.SUSPND = 0; while (UIRbits.ACTVIF) { UIRbits.ACTVIF = 0; } © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 hardware is synchronized may not have an effect on the value of ACTVIF. Additionally, if the USB module uses the clock from the 96 MHz PLL source, then after clearing the SUSPND bit, the USB module may not be immediately operational while waiting for the 96 MHz PLL to lock ...
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... PIC18F2455/2550/4455/4550 17.5.2 USB INTERRUPT ENABLE REGISTER (UIE) The USB Interrupt Enable register (Register 17-8) contains the enable bits for the USB status interrupt sources. Setting any of these bits will enable the respective interrupt source in the UIR register. REGISTER 17-8: UIE: USB INTERRUPT ENABLE REGISTER ...
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... PIDEF: PID Check Failure Flag bit 1 = PID check failed 0 = PID check passed © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Each error bit is set as soon as the error condition is detected. Thus, the interrupt will typically not correspond with the end of a token being processed. ...
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... PIC18F2455/2550/4455/4550 17.5.4 USB ERROR INTERRUPT ENABLE REGISTER (UEIE) The USB Error Interrupt Enable (Register 17-10) contains the enable bits for each of the USB error interrupt sources. Setting any of these bits will enable the respective error interrupt source in the UEIR register to propagate into the UERR bit at the top level of the interrupt logic ...
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... USB when no internal power is available. Figure 17-12 shows a simple Dual Power with Self-Power Dominance example, which automatically switches between Self-Power Only and USB Bus Power Only modes. © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 FIGURE 17-12: V BUS ~5V 100 kΩ ...
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... PIC18F2455/2550/4455/4550 17.8 Oscillator The USB module has specific clock requirements. For full-speed operation, the clock source must be 48 MHz. Even so, the microcontroller core and other peripherals are not required to run at that clock speed or even from the same clock source. Available clocking options are described in detail in Section 2.3 “ ...
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... FIGURE 17-13: USB LAYERS Interface Endpoint Endpoint © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 17.10.3 TRANSFERS There are four transfer types defined in the USB specification. • Isochronous: This type provides a transfer method for large amounts of data (up to 1023 bytes) with timely delivery ensured; ...
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... PIC18F2455/2550/4455/4550 The USB specification limits the power taken from the bus. Each device is ensured 100 mA at approximately 5V (one unit load). Additional power may be requested maximum of 500 mA. Note that power above one unit load is a request and the host or hub is not obligated to provide the extra current. Thus, a device ...
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... SPPEN: SPP Enable bit 1 = SPP is enabled 0 = SPP is disabled © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 In addition, the SPP can provide time multiplexed addressing information along with the data by using the second strobe output. Thus, the USB endpoint number can be written in conjunction with the data for that endpoint ...
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... PIC18F2455/2550/4455/4550 REGISTER 18-2: SPPCFG: SPP CONFIGURATION REGISTER R/W-0 R/W-0 R/W-0 CLKCFG1 CLKCFG0 CSEN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-6 CLKCFG1:CLKCFG0: SPP Clock Configuration bits 1x = CLK1 toggles on read or write of an Odd endpoint address; CLK2 toggles on read or write of an Even endpoint address 01 = CLK1 toggles on write ...
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... TIMING FOR USB WRITE ADDRESS AND READ DATA (4 WAIT STATES) USB Clock OESPP CSSPP CK1SPP CK2SPP Write Address SPP<7:0> 2 Wait States © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 DATA Write Data Read Data MOVF SPPDATA, W MOVWF SPPDATA Write Data 2 Wait States 2 Wait States Read Data ...
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... PIC18F2455/2550/4455/4550 18.2 Setup for USB Control When the SPP is configured for USB operation, data can be clocked directly to and from the USB peripheral without intervention of the microcontroller; thus, no process time is required. Data is clocked into or out from the SPP with endpoint (address) information first, followed by one or more bytes of data, as shown in Figure 18-5 ...
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... Endpoint Address 0 © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 3. Read the data from the SPPDATA register; the data from the previous read operation is returned. The SPP automatically starts the read cycle for the next read. 4. Monitor the SPPBUSY bit to determine when the data has been read ...
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... PIC18F2455/2550/4455/4550 TABLE 18-1: REGISTERS ASSOCIATED WITH THE STREAMING PARALLEL PORT Name Bit 7 Bit 6 (3) SPPCON — — (3) SPPCFG CLKCFG1 CLKCFG0 (3) SPPEPS RDSPP WRSPP (3) SPPDATA DATA7 DATA6 (3) PIR1 SPPIF ADIF (3) PIE1 SPPIE ADIE (3) IPR1 SPPIP ADIP (3) PORTE RDPU — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for the Streaming Parallel Port. ...
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... SPI mode. Additional details are provided under the individual sections. © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 19.3 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four modes of the SPI are supported. To accomplish communication, typically three pins are used: • ...
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... PIC18F2455/2550/4455/4550 19.3.1 REGISTERS The MSSP module has four registers for SPI mode operation. These are: • MSSP Control Register 1 (SSPCON1) • MSSP Status Register (SSPSTAT) • Serial Receive/Transmit Buffer Register (SSPBUF) • MSSP Shift Register (SSPSR) – Not directly accessible SSPCON1 and SSPSTAT are the control and status registers in SPI mode operation ...
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... In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 2: When enabled, these pins must be properly configured as input or output. 3: Bit combinations not specifically listed here are either reserved or implemented in I © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 R/W-0 R/W-0 R/W-0 CKP SSPM3 SSPM2 U = Unimplemented bit, read as ‘ ...
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... PIC18F2455/2550/4455/4550 19.3.2 OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPCON1<5:0> and SSPSTAT<7:6>). These control bits allow the following to be specified: • Master mode (SCK is the clock output) • Slave mode (SCK is the clock input) • ...
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... Shift Register (SSPSR) LSb MSb PROCESSOR 1 © 2007 Microchip Technology Inc. PIC18F2455/2550/4455/4550 19.3.4 TYPICAL CONNECTION Figure 19-2 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their programmed clock edge and latched on the opposite edge of the clock ...
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... PIC18F2455/2550/4455/4550 19.3.5 MASTER MODE The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 2, Figure 19- broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI is only going to receive, the SDO output could be dis- abled (programmed as an input) ...