PIC18F2525-I/SO Microchip Technology, PIC18F2525-I/SO Datasheet - Page 406
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PIC18F2525-I/SO
Manufacturer Part Number
PIC18F2525-I/SO
Description
IC MCU FLASH 24KX16 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2221-ISO.pdf
(46 pages)
2.PIC18F2525-ISO.pdf
(412 pages)
3.PIC18F2525-ISO.pdf
(18 pages)
4.PIC18F2525-ISO.pdf
(18 pages)
5.PIC18F2525-ISO.pdf
(6 pages)
6.PIC18F2525-ISO.pdf
(6 pages)
7.PIC18LF4620-IP.pdf
(390 pages)
Specifications of PIC18F2525-I/SO
Program Memory Type
FLASH
Program Memory Size
48KB (24K x 16)
Package / Case
28-SOIC (7.5mm Width)
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Eeprom Size
1K x 8
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3986 B
Interface Type
SPI, I2C, EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
25
Number Of Timers
1 x 8
Operating Supply Voltage
4.2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163022, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Package
28SOIC W
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MILI3DB18F4620 - BOARD DAUGHTER ICEPIC3
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F2525-I/SO
Manufacturer:
HITTITE
Quantity:
101
PIC18F2525/2620/4525/4620
Sleep
Software Simulator (MPLAB SIM) .................................... 318
Special Event Trigger. See Compare (ECCP Mode).
Special Event Trigger. See Compare (ECCP Module).
Special Features of the CPU ............................................ 249
Special Function Registers ................................................ 62
SPI Mode (MSSP)
SS .................................................................................... 161
SSPOV ............................................................................. 191
SSPOV Status Flag .......................................................... 191
SSPSTAT Register
Stack Full/Underflow Resets .............................................. 56
Standard Instructions ....................................................... 267
STATUS Register ............................................................... 66
SUBFSR ........................................................................... 313
SUBFWB .......................................................................... 302
SUBLW ............................................................................ 303
SUBULNK ........................................................................ 313
SUBWF ............................................................................ 303
SUBWFB .......................................................................... 304
SWAPF ............................................................................ 304
T
Table Reads/Table Writes .................................................. 56
TBLRD ............................................................................. 305
TBLWT ............................................................................. 306
Time-out in Various Situations (table) ................................ 45
Timer0 .............................................................................. 123
Timer1 .............................................................................. 127
DS39626E-page 404
OSC1 and OSC2 Pin States ...................................... 31
Map ............................................................................ 62
Associated Registers ............................................... 169
Bus Mode Compatibility ........................................... 169
Effects of a Reset ..................................................... 169
Enabling SPI I/O ...................................................... 165
Master Mode ............................................................ 166
Master/Slave Connection ......................................... 165
Operation ................................................................. 164
Operation in Power-Managed Modes ...................... 169
Serial Clock .............................................................. 161
Serial Data In ........................................................... 161
Serial Data Out ........................................................ 161
Slave Mode .............................................................. 167
Slave Select ............................................................. 161
Slave Select Synchronization .................................. 167
SPI Clock ................................................................. 166
Typical Connection .................................................. 165
R/W Bit ............................................................. 174, 175
Associated Registers ............................................... 125
Operation ................................................................. 124
Overflow Interrupt .................................................... 125
Prescaler .................................................................. 125
Prescaler Assignment (PSA Bit) .............................. 125
Prescaler Select (T0PS2:T0PS0 Bits) ..................... 125
Prescaler. See Prescaler, Timer0.
Reads and Writes in 16-Bit Mode ............................ 124
Source Edge Select (T0SE Bit) ................................ 124
Source Select (T0CS Bit) ......................................... 124
Switching Prescaler Assignment .............................. 125
16-Bit Read/Write Mode ........................................... 129
Associated Registers ............................................... 131
Interrupt .................................................................... 130
Operation ................................................................. 128
Oscillator .......................................................... 127, 129
Layout Considerations ..................................... 130
Low-Power Option ........................................... 129
Timer2 .............................................................................. 133
Timer3 .............................................................................. 135
Timing Diagrams
Overflow Interrupt .................................................... 127
Resetting, Using the CCP Special Event Trigger .... 130
Special Event Trigger (ECCP) ................................. 148
TMR1H Register ...................................................... 127
TMR1L Register ....................................................... 127
Use as a Real-Time Clock ....................................... 130
Associated Registers ............................................... 134
Interrupt ................................................................... 134
Operation ................................................................. 133
Output ...................................................................... 134
PR2 Register ................................................... 144, 149
TMR2 to PR2 Match Interrupt .......................... 144, 149
16-Bit Read/Write Mode .......................................... 137
Associated Registers ............................................... 137
Operation ................................................................. 136
Oscillator .......................................................... 135, 137
Overflow Interrupt ............................................ 135, 137
Special Event Trigger (CCP) ................................... 137
TMR3H Register ...................................................... 135
TMR3L Register ....................................................... 135
A/D Conversion ........................................................ 360
Acknowledge Sequence .......................................... 194
Asynchronous Reception ......................................... 214
Asynchronous Transmission .................................... 212
Asynchronous Transmission
Automatic Baud Rate Calculation ............................ 210
Auto-Wake-up Bit (WUE) During
Auto-Wake-up Bit (WUE) During Sleep ................... 215
Baud Rate Generator with Clock Arbitration ............ 188
BRG Overflow Sequence ......................................... 210
BRG Reset Due to SDA Arbitration
Brown-out Reset (BOR) ........................................... 345
Bus Collision During a Repeated
Bus Collision During a Repeated
Bus Collision During a Start
Bus Collision During a Stop
Bus Collision During a Stop
Bus Collision During Start
Bus Collision for Transmit and Acknowledge .......... 195
Capture/Compare/PWM (All CCP Modules) ............ 347
CLKO and I/O .......................................................... 344
Clock Synchronization ............................................. 181
Clock/Instruction Cycle .............................................. 57
EUSART Synchronous Receive
EUSART Synchronous Transmission
Example SPI Master Mode (CKE = 0) ..................... 349
Example SPI Master Mode (CKE = 1) ..................... 350
Example SPI Slave Mode (CKE = 0) ....................... 351
Example SPI Slave Mode (CKE = 1) ....................... 353
External Clock (All Modes Except PLL) ................... 342
Fail-Safe Clock Monitor ........................................... 262
(Back to Back) ................................................. 212
Normal Operation ............................................ 215
During Start Condition ..................................... 197
Start Condition (Case 1) .................................. 198
Start Condition (Case 2) .................................. 198
Condition (SCL = 0) ......................................... 197
Condition (Case 1) ........................................... 199
Condition (Case 2) ........................................... 199
Condition (SDA Only) ...................................... 196
(Master/Slave) ................................................. 359
(Master/Slave) ................................................. 358
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