PIC24HJ128GP504-I/ML Microchip Technology, PIC24HJ128GP504-I/ML Datasheet - Page 107

IC PIC MCU FLASH 128K 44QFN

PIC24HJ128GP504-I/ML

Manufacturer Part Number
PIC24HJ128GP504-I/ML
Description
IC PIC MCU FLASH 128K 44QFN
Manufacturer
Microchip Technology
Series
PIC® 24Hr

Specifications of PIC24HJ128GP504-I/ML

Core Size
16-Bit
Program Memory Size
128KB (43K x 24)
Oscillator Type
Internal
Core Processor
PIC
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
35
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 13x10b/12b
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Controller Family/series
PIC24
No. Of I/o's
35
Ram Memory Size
8192Byte
Cpu Speed
40MHz
No. Of Timers
7
No.
RoHS Compliant
Embedded Interface Type
CAN, I2C, SPI, UART
Rohs Compliant
Yes
Processor Series
PIC24HJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
35
Number Of Timers
9
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 13 Channel
A/d Bit Size
12 bit
A/d Channels Available
13
Height
0.88 mm
Length
8 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Width
8 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1004 - PIC24 BREAKOUT BOARDAC164336 - MODULE SOCKET FOR PM3 28/44QFNDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
8.1
Each DMAC Channel x (x = 0, 1, 2, 3, 4, 5, 6 or 7)
contains the following registers:
• A 16-bit DMA Channel Control register
• A 16-bit DMA Channel IRQ Select register
• A 16-bit DMA RAM Primary Start Address register
• A 16-bit DMA RAM Secondary Start Address
• A 16-bit DMA Peripheral Address register
• A 10-bit DMA Transfer Count register (DMAxCNT)
An additional pair of status registers, DMACS0 and
DMACS1, are common to all DMAC channels.
DMACS0 contains the DMA RAM and SFR write
collision flags, XWCOLx and PWCOLx, respectively.
DMACS1 indicates DMA channel and Ping-Pong mode
status.
© 2011 Microchip Technology Inc.
(DMAxCON)
(DMAxREQ)
(DMAxSTA)
register (DMAxSTB)
(DMAxPAD)
DMAC Registers
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04
The
DMAxCNT are all conventional read/write registers.
Reads of DMAxSTA or DMAxSTB reads the contents
of the DMA RAM Address register. Writes to
DMAxSTA or DMAxSTB write to the registers. This
allows the user to determine the DMA buffer pointer
value (address) at any time.
The interrupt flags (DMAxIF) are located in an IFSx
register in the interrupt controller. The corresponding
interrupt enable control bits (DMAxIE) are located in
an IECx register in the interrupt controller, and the
corresponding interrupt priority control bits (DMAxIP)
are located in an IPCx register in the interrupt
controller.
DMAxCON,
DMAxREQ,
DS70293E-page 107
DMAxPAD
and

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