PIC24HJ128GP504-I/ML Microchip Technology, PIC24HJ128GP504-I/ML Datasheet - Page 63

IC PIC MCU FLASH 128K 44QFN

PIC24HJ128GP504-I/ML

Manufacturer Part Number
PIC24HJ128GP504-I/ML
Description
IC PIC MCU FLASH 128K 44QFN
Manufacturer
Microchip Technology
Series
PIC® 24Hr

Specifications of PIC24HJ128GP504-I/ML

Core Size
16-Bit
Program Memory Size
128KB (43K x 24)
Oscillator Type
Internal
Core Processor
PIC
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
35
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 13x10b/12b
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Controller Family/series
PIC24
No. Of I/o's
35
Ram Memory Size
8192Byte
Cpu Speed
40MHz
No. Of Timers
7
No.
RoHS Compliant
Embedded Interface Type
CAN, I2C, SPI, UART
Rohs Compliant
Yes
Processor Series
PIC24HJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
35
Number Of Timers
9
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 13 Channel
A/d Bit Size
12 bit
A/d Channels Available
13
Height
0.88 mm
Length
8 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Width
8 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1004 - PIC24 BREAKOUT BOARDAC164336 - MODULE SOCKET FOR PM3 28/44QFNDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
FIGURE 6-2:
© 2011 Microchip Technology Inc.
Oscillator Clock
Device Status
Note 1: POR: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is active
SYSRST
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04
FSCM
POR
BOR
V
DD
2: BOR: The on-chip voltage regulator has a BOR circuit that keeps the device in Reset until V
3: PWRT Timer: The programmable power-up timer continues to hold the processor in Reset for a specific
4: Oscillator Delay: The total delay for the clock to be ready for various clock source selections are given in
5: When the oscillator clock is ready, the processor begins execution from location 0x000000. The user
6: The Fail-Safe Clock Monitor (FSCM), if enabled, begins to monitor the system clock when the system clock
until V
V
becomes stable.
period of time (T
at the appropriate level for full-speed operation. After the delay T
inactive, which in turn enables the selected oscillator to start generating clock cycles.
Table
application programs a GOTO instruction at the reset address, which redirects program execution to the
appropriate start-up routine.
is ready and the delay T
BOR
1
SYSTEM RESET TIMING
6-1. Refer to
DD
threshold and the delay T
crosses the V
2
T
PWRT
V
POR
POR
Section 9.0 “Oscillator Configuration”
) after a BOR. The delay T
POR
FSCM
threshold and the delay T
elapsed.
BOR
Vbor
V
BOR
has elapsed. The delay T
T
PWRT
T
3
BOR
Reset
Time
PWRT
ensures that the system power supplies have stabilized
POR
T
OSCD
has elapsed.
for more information.
BOR
PWRT
T
OST
ensures the voltage regulator output
4
has elapsed, the SYSRST becomes
T
LOCK
DS70293E-page 63
5
DD
6
Run
crosses the
T
FSCM

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