PIC18LF2320-I/SP Microchip Technology, PIC18LF2320-I/SP Datasheet - Page 257
![IC MCU FLASH 4KX16 EEPROM 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC18LF2320-I/SP
Manufacturer Part Number
PIC18LF2320-I/SP
Description
IC MCU FLASH 4KX16 EEPROM 28DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2220-ISO.pdf
(394 pages)
3.PIC18F2220-ISO.pdf
(6 pages)
4.PIC18F2220-ISO.pdf
(6 pages)
5.PIC18F2220-ISO.pdf
(8 pages)
6.PIC18F2220-ISO.pdf
(6 pages)
7.PIC18F2220-ISO.pdf
(6 pages)
Specifications of PIC18LF2320-I/SP
Core Size
8-Bit
Program Memory Size
8KB (4K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
No. Of I/o's
25
Eeprom Memory Size
256Byte
Ram Memory Size
512Byte
Cpu Speed
40MHz
No. Of Timers
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC18F2220-ISO PDF datasheet #2
- PIC18F2220-ISO PDF datasheet #3
- PIC18F2220-ISO PDF datasheet #4
- PIC18F2220-ISO PDF datasheet #5
- PIC18F2220-ISO PDF datasheet #6
- PIC18F2220-ISO PDF datasheet #7
- Current page: 257 of 394
- Download datasheet (7Mb)
23.5.2
The entire data EEPROM is protected from external
reads and writes by two bits: CPD and WRTD. CPD
inhibits external reads and writes of data EEPROM.
WRTD inhibits external writes to data EEPROM. The
CPU can continue to read and write data EEPROM
regardless of the protection bit settings.
23.5.3
The Configuration registers can be write-protected.
The WRTC bit controls protection of the Configuration
registers. In normal execution mode, the WRTC bit is
readable only. WRTC can only be written via ICSP or
an external programmer.
23.6
Eight memory locations (200000h-200007h) are desig-
nated as ID locations, where the user can store check-
sum or other code identification numbers. These
locations are both readable and writable during normal
execution through the TBLRD and TBLWT instructions,
or during program/verify. The ID locations can be read
when the device is code-protected.
23.7
PIC18F2X20/4X20 microcontrollers can be serially
programmed while in the end application circuit. This is
simply done with two lines for clock and data and three
other lines for power, ground and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom
firmware to be programmed (see Table 23-5).
23.8
When the DEBUG bit in Configuration register,
CONFIG4L, is programmed to a ‘0’, the In-Circuit
Debugger functionality is enabled. This function allows
simple debugging functions when used with MPLAB
IDE. When the microcontroller has this feature
enabled, some resources are not available for general
use. Table 23-4 shows which resources are required by
the background debugger.
TABLE 23-4:
© 2007 Microchip Technology Inc.
I/O pins:
Stack:
Program Memory:
Data Memory:
ID Locations
In-Circuit Debugger
In-Circuit Serial Programming
DATA EEPROM
CODE PROTECTION
CONFIGURATION REGISTER
PROTECTION
DEBUGGER RESOURCES
RB6, RB7
2 levels
512 bytes
10 bytes
PIC18F2220/2320/4220/4320
®
To use the In-Circuit Debugger function of the micro-
controller, the design must implement In-Circuit Serial
Programming connections to MCLR/V
RB7 and RB6. This will interface to the In-Circuit
Debugger module available from Microchip or one of
the third party development tool companies.
23.9
The
(CONFIG4L<2>) enables Low-Voltage ICSP Program-
ming (LVP). When LVP is enabled, the microcontroller
can be programmed without requiring high voltage
being applied to the MCLR/V
pin is then dedicated to controlling Program mode entry
and is not available as a general purpose I/O pin.
LVP is enabled in erased devices.
While programming using LVP, V
MCLR/V
Programming mode, V
If Low-Voltage ICSP Programming mode will not be
used, the LVP bit can be cleared and RB5/PGM
becomes available as the digital I/O pin, RB5. The LVP
bit may be set or cleared only when using standard
high-voltage programming (V
V
dard high-voltage programming is available and must
be used to program the device.
Memory that is not code-protected can be erased using
either a block erase, or erased row by row, then written
at any specified V
erased, a block erase is required. If a block erase is to
be performed when using Low-Voltage Programming,
the device must be supplied with V
TABLE 23-5:
PP
Signal
MCLR
PGM
PGD
PGC
Note 1: High-voltage programming is always
V
V
pin). Once LVP has been disabled, only the stan-
DD
SS
LVP
PP
2: When
3: When LVP is enabled, externally pull the
Low-Voltage ICSP Programming
pin as in normal execution mode. To enter
available, regardless of the state of the
LVP bit or the PGM pin, by applying V
to the MCLR pin.
enabled, the RB5 pin can no longer be
used as a general purpose I/O pin.
PGM pin to V
execution.
MCLR
RB7
RB6
RB5
V
bit
V
Pin
DD
SS
DD
ICSP™/ICD CONNECTIONS
in
. If code-protected memory is to be
Low-Voltage
May require isolation from
application circuits
Pull RB5 low if LVP is enabled
DD
Configuration
is applied to the PGM pin.
SS
PP
to allow normal program
IHH
pin, but the RB5/PGM
applied to the MCLR/
DD
Notes
DD
DS39599G-page 255
Programming
is applied to the
of 4.5V to 5.5V.
PP
Register
, V
DD
, V
IHH
SS
4L
is
,
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