AT89C5132-ROTUL Atmel, AT89C5132-ROTUL Datasheet - Page 143

• Manufacturer Part Number: AT89C5132-ROTUL
• Description: IC 8051 MCU FLASH 64K USB 80TQFP
• Manufacturer: Atmel
• Series: AT89C513xr

Specifications of AT89C5132-ROTUL

• Core Processor: C52X2
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: IDE/ATAPI, I²C, MMC, PCM, SPI, UART/USART, USB
• Peripherals: I²S, POR, WDT
• Number Of I /o: 44
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Cpu Family: 89C
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: IDE/SPI/UART/USB
• Total Internal Ram Size: 2.25KB
• # I/os (max): 44
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 2-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: TQFP
• Package: 80TQFP
• Family Name: 89C
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 44
• Number Of Timers: 2
• Maximum Clock Frequency: 20 MHz
• Data Ram Size: 2304 B
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 2
• Height: 1.45 mm
• Length: 14.1 mm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 2.7 V
• Width: 14.1 mm
• For Use With: AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 23. Status for Slave Receiver Mode with General Call Address
4173E–USB–09/07
SSSTA
Status
Code
A0h
70h
78h
90h
98h
Status of the TWI Bus
and TWI Hardware
General call address
has been received;
ACK has been
returned
Arbitration lost in
SLA+R/W as master;
general call address
has been received;
ACK has been
returned
Previously addressed
with general call; data
has been received;
ACK has been
returned
Previously addressed
with general call; data
has been received;
NOT ACK has been
returned
A STOP condition or
repeated START
condition has been
received while still
addressed as slave
To/From SSDAT
No SSDAT action
No SSDAT action
No SSDAT action
No SSDAT action
Read data Byte
Read data Byte
Read data Byte
Read data Byte
Read data Byte
Read data Byte
No SSDAT action
No SSDAT action
No SSDAT action
No SSDAT action
Application Software Response
SSSTA
X
X
X
X
X
X
0
0
1
1
0
0
1
1
SSSTO
To SSCON
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SSI
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SSAA
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Next Action Taken by TWI Hardware
Data Byte will be received and NOT ACK will be
returned.
Data Byte will be received and ACK will be returned.
Data Byte will be received and NOT ACK will be
returned.
Data Byte will be received and ACK will be returned.
Data Byte will be received and NOT ACK will be
returned.
Data Byte will be received and ACK will be returned.
Switched to the not addressed slave mode; no
recognition of own SLA or GCA.
Switched to the not addressed slave mode; own
SLA will be recognized; GCA will be recognized if
SSGC = logic 1.
Switched to the not addressed slave mode; no
recognition of own SLA or GCA. A START condition
will be transmitted when the bus becomes free.
Switched to the not addressed slave mode; own
SLA will be recognized; GCA will be recognized if
SSGC = logic 1. A START condition will be
transmitted when the bus becomes free.
Switched to the not addressed slave mode; no
recognition of own SLA or GCA.
Switched to the not addressed slave mode; own
SLA will be recognized; GCA will be recognized if
SSGC = logic 1.
Switched to the not addressed slave mode; no
recognition of own SLA or GCA. A START condition
will be transmitted when the bus becomes free.
Switched to the not addressed slave mode; own
SLA will be recognized; GCA will be recognized if
SSGC = logic 1. A START condition will be
transmitted when the bus becomes free.
AT89C5132
143