DSPIC30F6010-30I/PF Microchip Technology, DSPIC30F6010-30I/PF Datasheet - Page 2

• Manufacturer Part Number: DSPIC30F6010-30I/PF
• Description: IC DSPIC MCU/DSP 144K 80TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F6010-30I/PF

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 144KB (48K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 68
• Flash Memory Size: 144KB
• Supply Voltage Range: 2.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300019 - BOARD DEMO DSPICDEM 80L STARTERAC164314 - MODULE SKT FOR PM3 80PFDM300020 - BOARD DEV DSPICDEM MC1 MOTORCTRLAC30F001 - MODULE SOCKET DSPIC30F 80TQFPXLT80PT2 - SOCKET TRANSITION ICE 80TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F601030IPF

dsPIC30F6010
10. DISI Instruction
11. 32-bit General Purpose Timers
12. Output Compare Module in PWM Mode
13. Output Compare Module
14. Quadrature Encoder Interface – Index Pulse
15. 10-bit Analog-to-Digital Converter (ADC) –
16. 10-bit A/D Converter – Gain Error
17. Motor Control PWM – Time Base Prescaler
18. Motor Control PWM – Output Override
19. Motor Control PWM – Output Override
20. Motor Control PWM – Dead Time Generators
21. CAN SFR Reads
DS80195H-page 2
The DISI instruction will not disable interrupts if a
DISI instruction is executed in the same
instruction
decrements to zero.
The 32-bit general purpose timers do not function
as specified for prescaler ratios other than 1:1.
Output compare will produce a glitch when loading
0% duty cycle in PWM mode. It will also miss the
next compare after the glitch.
The output compare module will produce a glitch
on the output when an I/O pin is initially set high
and the module is configured to drive the pin low at
a specified time.
The Reset on Index Pulse mode does not work.
Sequential Sampling
Sampling multiple channels sequentially using any
conversion trigger other than the auto-convert
feature requires SAMC bits to be non-zero.
The 10-bit ADC exhibits a maximum gain error of
+/-3 Least Significant bits (LSbs).
The Motor Control PWM time base prescaler
options, 1:4, 1:16 and 1:64, may produce
unexpected results when used to generate PWM
pulses.
The output override function of the PWM module,
controlled by the OVDCON register and the
OSYNC
unexpected results when OSYNC = 1.
Synchronization
Unexpected results may occur when the OSYNC
bit <PWMCON2<1>) is set.
Unexpected output results may occur if the motor
control PWM is operated in Complementary mode
with dead time and the duty cycle near 0% or
100%.
Read operations performed on CAN module
Special Function Registers (SFRs), may yield
incorrect results at operation over 20 MIPS.
(PWMCON2<1>)
cycle
that
the
bit,
DISI
produces
counter
22. High I
23. Regulating Voltage for 5V/30 MIPS Applications
24. 4x PLL Operation
25. Sequential Interrupts
26. 8x PLL Mode
27. Quadrature Encoder Interface (QEI) Module
28. CAN Module
29. Sleep Mode
30. I
31. Motor Control PWM – PWM Counter Register
32. I/O Port – Port Pin Multiplexed with IC1
33. I
Memory
This release of silicon exhibits a current draw (I
of approximately 370 mA during a Row Erase
operation performed on program Flash memory.
For this release of silicon, applications operating
off 5 volts V
remains between 4.75V and 5.5V.
The 4x PLL mode of operation may not function
correctly for certain input frequencies.
Sequential interrupts after modifying the CPU IPL,
interrupt IPL, interrupt enable or interrupt flag may
cause an address error trap.
If 8x PLL mode is used, the input frequency range
is 5 MHz-10 MHz instead of 4 MHz-10 MHz.
The QEI module does not generate an interrupt in
a particular overflow condition.
The CAN module does not cause a filter match
with filters 3, 4 and 5 at a baud rate of more than
500 kbps.
Execution of the Sleep instruction (PWRSAV #0)
may cause incorrect program operation after the
device wakes up from Sleep. The current
consumption during Sleep may also increase
beyond the specifications listed in the device data
sheet.
The I
operating as an I
PTMR does not continue counting down after
halting code execution in Debug mode.
The port I/O pin multiplexed with the Input Capture
1 (IC1) function cannot be used as a digital input
pin when the UART auto-baud feature is enabled.
When the I
addressing using the same address bits (A10 and
A9) as other I
not work as expected.
2
2
C™ Module
C Module: 10-bit addressing mode
2
DD
C module loses incoming data bytes when
During Row Erase of Program Flash
DD
2
2
C module is configured for 10-bit
C devices, the A10 and A9 bits may
at 30 MIPS should ensure the V
2
C slave.
© 2008 Microchip Technology Inc.
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