DSPIC30F6010-30I/PF Microchip Technology, DSPIC30F6010-30I/PF Datasheet
DSPIC30F6010-30I/PF
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DSPIC30F6010-30I/PF Summary of contents
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... Microchip Technology Inc. dsPIC30F6010 Data Sheet High-Performance, 16-Bit Digital Signal Controllers DS70119E ...
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... Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Enhanced Flash 16-Bit Digital Signal Controller Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “ ...
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... This table provides a summary of the dsPIC30F6010 peripheral features. Other available devices in the dsPIC30F Motor Control and Power Conversion Family are shown for feature comparison. DS70119E-page 2 • Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) • ...
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... PWM4H/RE7 4 T2CK/RC1 5 T4CK/RC3 SCK2/CN8/RG6 6 SDI2/CN9/RG7 7 SDO2/CN10/RG8 8 MCLR 9 SS2/CN11/RG9 FLTA/INT1/RE8 13 FLTB/INT2/RE9 14 AN5/QEB/CN7/RB5 15 AN4/QEA/CN6/RB4 16 AN3/INDX/CN5/RB3 17 AN2/SS1/LVDIN/CN4/RB2 18 PGC/EMUC/AN1/CN3/RB1 19 PGD/EMUD/AN0/CN2/RB0 20 *dsPIC30F6010A recommended for new designs. © 2006 Microchip Technology Inc. dsPIC30F6010 dsPIC30F6010 EMUC1/SOSCO/T1CK/CN0/RC14 EMUD1/SOSCI/CN1/RC13 EMUC2/OC1/RD0 IC4/RD11 IC3/RD10 IC2/RD9 IC1/RD8 INT4/RA15 INT3/RA14 V SS OSC2/CLKO/RC15 OSC1/CLKI V DD ...
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... Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 5 2.0 CPU Architecture Overview........................................................................................................................................................ 11 3.0 Memory Organization ................................................................................................................................................................. 19 4.0 Address Generator Units ............................................................................................................................................................ 31 5.0 Interrupts .................................................................................................................................................................................... 37 6.0 Flash Program Memory .............................................................................................................................................................. 43 7.0 Data EEPROM Memory ............................................................................................................................................................. 49 8.0 I/O Ports ..................................................................................................................................................................................... 53 9.0 Timer1 Module ........................................................................................................................................................................... 57 10.0 Timer2/3 Module ........................................................................................................................................................................ 61 11.0 Timer4/5 Module ....................................................................................................................................................................... 67 12.0 Input Capture Module ................................................................................................................................................................ 71 13 ...
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... Programmer’s Reference Manual” (DS70157). © 2006 Microchip Technology Inc. dsPIC30F6010 This document contains device specific information for the dsPIC30F6010 device. The dsPIC30F devices contain extensive Digital Signal Processor (DSP) func- tionality within a high-performance 16-bit microcontroller (MCU) architecture. Figure 1-1 shows a device block diagram for the dsPIC30F6010 device ...
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... FIGURE 1-1: dsPIC30F6010 BLOCK DIAGRAM Y Data Bus Interrupt PSV & Table Controller Data Access 8 24 Control Block 24 24 PCU PCH Program Counter Stack Address Latch Control Control Logic Program Memory (144 Kbytes) Data EEPROM (4 Kbytes) 16 Data Latch ROM Latch 24 IR ...
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... Table 1-1 provides a brief description of the device I/O pinout and the functions that are multiplexed to a port pin. Multiple functions may exist on one port pin. When TABLE 1-1: DSPIC30F6010 I/O PIN DESCRIPTIONS Pin Buffer Pin Name Type Type AN0-AN15 I Analog CLKI ...
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... TABLE 1-1: DSPIC30F6010 I/O PIN DESCRIPTIONS (CONTINUED) Pin Buffer Pin Name Type Type FLTA I ST FLTB I ST PWM1L O — PWM1H O — PWM2L O — PWM2H O — PWM3L O — PWM3H O — PWM4L O — PWM4H O — MCLR I/P ST OCFA I ST OCFB I ST OC1-OC8 O — ...
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... TABLE 1-1: DSPIC30F6010 I/O PIN DESCRIPTIONS (CONTINUED) Pin Buffer Pin Name Type Type U1RX I ST U1TX O — U2RX I ST U2TX O — — — Analog REF Analog REF Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input © 2006 Microchip Technology Inc. ...
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... NOTES: DS70119E-page 10 © 2006 Microchip Technology Inc. ...
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... Programmer’s Reference Manual” (DS70157). This document provides a summary dsPIC30F6010 CPU and peripheral function. For a complete description of this functionality, please refer to the “dsPIC30F Family Reference Manual” (DS70046). 2.1 Core Overview The core has a 24-bit instruction word. The Program Counter (PC bits wide with the Least Significant bit (LSb) always clear (see Section 3.1 “ ...
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... Programmer’s Model The programmer’s model is shown in Figure 2-1 and consists of 16x16-bit working registers (W0 through W15), 2x40-bit accumulators (ACCA and ACCB), STATUS register (SR), Data Table Page register (TBLPAG), Program Space Visibility Page register (PSVPAG), DO and REPEAT registers (DOSTART, DOEND, DCOUNT and RCOUNT), and Program Counter (PC) ...
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... FIGURE 2-1: dsPIC30F6010 PROGRAMMER’S MODEL DSP Operand Registers DSP Address Registers AD39 DSP ACCA Accumulators ACCB PC22 7 0 TABPAG TBLPAG Data Table Page Address 7 0 PSVPAG PSVPAG OAB SAB DA SRH © 2006 Microchip Technology Inc. D15 D0 W0/WREG W10 W11 W12/DSP Offset ...
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... Divide Support The dsPIC DSC devices feature a 16/16-bit signed fractional divide operation, as well as 32/16-bit and 16/ 16-bit signed and unsigned integer divide operations, in the form of single instruction iterative divides. The fol- lowing instructions and data sizes are supported: 1. DIVF – 16/16 signed fractional divide 2. DIV.sd – ...
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... FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In © 2006 Microchip Technology Inc. 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-bit Multiplier/Scaler 16 16 To/From W Array dsPIC30F6010 Round u Logic Zero Backfill DS70119E-page 15 ...
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... MULTIPLIER The 17x17-bit multiplier is capable of signed or unsigned operation and can multiplex its output using a scaler to support either 1.31 fractional (Q31) or 32-bit integer results. Unsigned operands are zero-extended into the 17th bit of the multiplier input value. Signed operands are sign-extended into the 17th bit of the mul- tiplier input value ...
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... If the COVTE bit in the INTCON1 register is set, a catastrophic overflow can initiate a trap exception. © 2006 Microchip Technology Inc. dsPIC30F6010 2.4.2.2 Accumulator ‘Write Back’ The MAC class of instructions (with the exception of MPY, MPY.N, ED and EDAC) can optionally write a ...
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... Data Space Write Saturation In addition to adder/subtracter saturation, writes to data space may also be saturated, but without affecting the contents of the source accumulator. The data space write saturation logic block accepts a 16-bit, 1.15 frac- tional value from the round logic block as its input, together with overflow status from the original source (accumulator) and the 16-bit round adder ...
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... Device ID, the User ID and the Configuration bits. Otherwise, bit 23 is always clear. © 2006 Microchip Technology Inc. dsPIC30F6010 FIGURE 3-1: PROGRAM SPACE MEMORY MAP FOR dsPIC30F6010 Reset - GOTO Instruction Reset - Target Address Interrupt Vector Table Reserved Alternate Vector Table User Flash Program Memory ...
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... TABLE 3-1: PROGRAM SPACE ADDRESS CONSTRUCTION Access Access Type Space Instruction Access User User TBLRD/TBLWT (TBLPAG<7> Configuration TBLRD/TBLWT (TBLPAG<7> Program Space Visibility User FIGURE 3-2: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION Using Program 0 Counter Using 0 PSVPAG Reg Program Space ...
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... Program Memory ‘Phantom’ Byte (Read as ‘0’). © 2006 Microchip Technology Inc. dsPIC30F6010 A set of Table Instructions are provided to move byte or word sized data to and from program space. 1. TBLRDL: Table Read Low Word: Read the least significant word of the program address ...
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... FIGURE 3-4: PROGRAM DATA TABLE ACCESS (MOST SIGNIFICANT BYTE) PC Address 0x000000 00000000 0x000002 00000000 00000000 0x000004 0x000006 00000000 Program Memory ‘Phantom’ Byte (Read as ‘0’) 3.1.2 DATA ACCESS FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into any 16K word program space page ...
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... The data space memory is split into two blocks, X and Y data space. A key element of this architecture is that Y space is a subset of X space, and is fully contained within X space. In order to provide an apparent linear addressing space, X and Y spaces have contiguous addresses. © 2006 Microchip Technology Inc. dsPIC30F6010 Program Space 0x0000 (1) PSVPAG 0x00 8 ...
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... FIGURE 3-6: dsPIC30F6010 DATA SPACE MEMORY MAP MSB Address 0x0001 2 Kbyte SFR Space 0x07FF 0x0801 8 Kbyte 0x17FF 0x1801 SRAM Space 0x1FFF 0x27FF 0x2801 0x8001 Optionally Mapped into Program Memory 0xFFFF DS70119E-page 24 LSB 16 bits Address MSB LSB 0x0000 SFR Space 0x07FE ...
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... DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE SFR SPACE (Y SPACE) Non-MAC Class Ops (Read/Write) MAC Class Ops (Write) Indirect EA using any W © 2006 Microchip Technology Inc. dsPIC30F6010 SFR SPACE UNUSED Y SPACE UNUSED UNUSED MAC Class Ops Read Only ...
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... DATA SPACES The X data space is used by all instructions and sup- ports all addressing modes. There are separate read and write data buses. The X read data bus is the return data path for all instructions that view data space as combined X and Y address space also the X address space data path for the dual operand read instructions (MAC class) ...
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... A PC push during exception processing will concatenate the SRL register to the MSB of the PC prior to the push. © 2006 Microchip Technology Inc. dsPIC30F6010 There is a Stack Pointer Limit register (SPLIM) associ- ated with the Stack Pointer. SPLIM is uninitialized at Reset the case for the Stack Pointer, SPLIM<0> ...
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TABLE 3-3: CORE REGISTER MAP Address SFR Name Bit 15 Bit 14 Bit 13 Bit 12 (Home) W0 0000 W1 0002 W2 0004 W3 0006 W4 0008 W5 000A W6 000C W7 000E W8 0010 W9 0012 W10 0014 W11 ...
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TABLE 3-3: CORE REGISTER MAP (CONTINUED) Address SFR Name Bit 15 Bit 14 Bit 13 Bit 12 (Home) CORCON 0044 — — — US MODCON 0046 XMODEN YMODEN — XMODSRT 0048 XMODEND 004A YMODSRT 004C YMODEND 004E XBREV 0050 BREN ...
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... NOTES: DS70119E-page 30 © 2006 Microchip Technology Inc. ...
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... The contents of a register are accessed directly. The contents of Wn forms the EA. The contents of Wn forms the EA post-modified (incremented or decremented constant value pre-modified (incremented or decremented signed constant value to form the EA. The sum of Wn and a literal forms the EA. dsPIC30F6010 following addressing modes are modes given above ...
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... MOVE AND ACCUMULATOR INSTRUCTIONS Move instructions and the DSP Accumulator class of instructions provide a greater degree of addressing flexibility than other instructions. In addition to the addressing modes supported by most MCU instruc- tions, Move and Accumulator instructions also support Register Indirect with Register Offset Addressing mode, also referred to as Register Indexed mode ...
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... Address 0x1100 0x1163 Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words © 2006 Microchip Technology Inc. dsPIC30F6010 4.2.2 W ADDRESS REGISTER SELECTION The Modulo and Bit-Reversed Addressing Control reg- ister MODCON<15:0> contains enable flags as well register field to specify the W address registers. ...
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... MODULO ADDRESSING APPLICABILITY Modulo Addressing can be applied to the effective address (EA) calculation associated with any W regis- ter important to realize that the address bound- aries check for addresses less than or greater than the upper (for incrementing buffers) and lower (for decre- menting buffers) boundary addresses (not just equal to) ...
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... BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER Buffer Size (Words) 4096 2048 1024 512 256 128 © 2006 Microchip Technology Inc. Bit-Reversed Address Decimal XB<14:0> Bit-Reversed Address Modifier Value dsPIC30F6010 A0 Decimal 0x0800 0x0400 0x0200 0x0100 0x0080 0x0040 0x0020 0x0010 0x0008 0x0004 0x0002 0x0001 DS70119E-page 35 ...
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... NOTES: DS70119E-page 36 © 2006 Microchip Technology Inc. ...
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... Manual” (DS70046). For more information on the device instruction set and programming, refer to the “dsPIC30F/ 33F Programmer’s Reference Manual” (DS70157). The dsPIC30F6010 has 44 interrupt sources and 4 processor exceptions (traps), which must be arbitrated based on a priority scheme. The CPU is responsible for reading the Interrupt Vec- tor Table (IVT) and transferring the address contained in the interrupt vector to the program counter ...
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... Interrupt Priority The user assignable Interrupt Priority (IP<2:0>) bits for each individual interrupt source are located in the Least Significant 3 bits of each nibble, within the IPCx regis- ter(s). Bit 3 of each nibble is not used and is read as a ‘0’. These bits define the priority level assigned to a particular interrupt by the user ...
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... Trap Lockout: Occurrence of multiple Trap conditions simultaneously will cause a Reset. © 2006 Microchip Technology Inc. dsPIC30F6010 5.3 Traps Traps can be considered as non-maskable interrupts indicating a software or hardware error, which adhere to a predefined priority as shown in Figure 5-1. They ...
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... Address Error Trap: This trap is initiated when any of the following circumstances occurs misaligned data word access is attempted data fetch from our unimplemented data memory location is attempted data access of an unimplemented program memory location is attempted instruction fetch from vector space is attempted. ...
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... If an enabled interrupt request of sufficient priority is received by the interrupt controller, then the standard interrupt request is presented to the processor. At the same time, the processor will wake-up from Sleep or Idle and begin execution of the Interrupt Service Routine (ISR) needed to process the interrupt request. dsPIC30F6010 DS70119E-page 41 ...
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TABLE 5-2: INTERRUPT CONTROLLER REGISTER MAP SFR ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name INTCON1 0080 NSTDIS — — — — INTCON2 0082 ALTIVT — — — — IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ADIF ...
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... Addressing Using Table Instruction User/Configuration Space Select © 2006 Microchip Technology Inc. dsPIC30F6010 6.2 Run-Time Self-Programming (RTSP) RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may erase program memory, 32 instructions (96 bytes time and can write program memory data, 32 instructions (96 bytes time ...
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... RTSP Operation The dsPIC30F Flash program memory is organized into rows and panels. Each row consists of 32 instruc- tions bytes. Each panel consists of 128 rows instructions. RTSP allows the user to erase one row (32 instructions time and to program 32 instructions at one time. ...
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... MOV W1 NVMKEY , BSET NVMCON,#WR NOP NOP © 2006 Microchip Technology Inc. dsPIC30F6010 4. Write 32 instruction words of data from data RAM “image” into the program Flash write latches. 5. Program 32 instruction words into program Flash. a) Setup NVMCON register for multi-word, program Flash, program, and set WREN bit ...
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... LOADING WRITE LATCHES Example 6-2 shows a sequence of instructions that can be used to load the 96 bytes of write latches. 32 TBLWTL and 32 TBLWTH instructions are needed to load the write latches selected by the table pointer. EXAMPLE 6-2: LOADING WRITE LATCHES ; Set up a pointer to the first program memory location to be written ...
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TABLE 6-1: NVM REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 NVMCON 0760 WR WREN WRERR NVMADR 0762 NVMADRU 0764 — — — NVMKEY 0766 — — — Legend: ...
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... NOTES: DS70119E-page 48 © 2006 Microchip Technology Inc. ...
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... NVMADRU register, is used to address the EEPROM location being accessed. TBLRDL and TBLWTL instruc- tions are used to read and write data EEPROM. The dsPIC30F6010 device has 8 Kbytes (4K words) of data EEPROM, with an address range from 0x7FF000 to 0x7FFFFE. A word write operation should be preceded by an erase of the corresponding memory location(s) ...
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... Erasing Data EEPROM 7.2.1 ERASING A BLOCK OF DATA EEPROM In order to erase a block of data EEPROM, the NVMADRU and NVMADR registers must initially point to the block of memory to be erased. Configure NVMCON for erasing a block of data EEPROM, and set the ERASE and WREN bits in NVMCON register. ...
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... Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle ; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete © 2006 Microchip Technology Inc. dsPIC30F6010 The write will not initiate if the above sequence is not exactly followed (write 0x55 to NVMKEY, write 0xAA to NVMCON, then set WR bit) for each word ...
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... WRITING A BLOCK OF DATA EEPROM To write a block of data EEPROM, write to all sixteen latches first, then set the NVMCON register and program the block. EXAMPLE 7-5: DATA EEPROM BLOCK WRITE MOV #LOW_ADDR_WORD,W0 MOV #HIGH_ADDR_WORD,W1 MOV W1 TBLPAG , MOV #data1,W2 [ W0]++ TBLWTL W2 , MOV #data2,W2 ...
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... I/O cell (pad) to which they are connected. Table 8-1 shows the formats of the registers for the shared ports, PORTB through PORTG. Dedicated Port Module Read TRIS TRIS Latch Data Latch dsPIC30F6010 pins. The LATA register supplies REF I/O Cell I/O Pad DS70119E-page 53 ...
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... FIGURE 8-2: BLOCK DIAGRAM OF A SHARED PORT STRUCTURE Peripheral Module Peripheral Input Data Peripheral Module Enable Peripheral Output Enable Peripheral Output Data PIO Module Read TRIS Data Bus WR TRIS TRIS Latch WR LAT + WR Port Data Latch Read LAT Read Port 8.2 ...
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... TABLE 8-1: dsPIC30F6010 PORT REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name TRISA 02C0 TRISA15 TRISA14 — — PORTA 02C2 RA15 RA14 — — LATA 02C4 LATA15 LATA14 — — TRISB 02C6 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 ...
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... Input Change Notification Module The Input Change Notification module provides the dsPIC30F devices the ability to generate interrupt requests to the processor in response to a change-of- state on selected input pins. This module is capable of detecting input change-of-states even in Sleep mode, when the clocks are disabled. There are 22 external ...
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... Interrupt on 16-bit period register match or falling edge of external gate signal © 2006 Microchip Technology Inc. dsPIC30F6010 These operating modes are determined by setting the appropriate bit(s) in the 16-bit SFR, T1CON. Figure 9-1 presents a block diagram of the 16-bit timer module. 16-bit Timer Mode: In the 16-bit Timer mode, the timer ...
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... FIGURE 9-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM (TYPE A TIMER) Equal Reset 0 T1IF Event Flag 1 TGATE SOSCO/ T1CK LPOSCEN SOSCI 9.1 Timer Gate Operation The 16-bit timer can be placed in the Gated Time Accu- mulation mode. This mode allows the internal T increment the respective timer when the gate input sig- nal (T1CK pin) is asserted high. Control bit TGATE (T1CON< ...
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... XTAL SOSCO pF 100K © 2006 Microchip Technology Inc. dsPIC30F6010 9.5.1 RTC OSCILLATOR OPERATION When the TON = 1, TCS = 1 and TGATE = 0, the timer increments on the rising edge of the 32 kHz LP oscilla- tor output signal the value specified in the period register, and is then reset to ‘0’. ...
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TABLE 9-1: TIMER1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — Legend uninitialized bit Note: Refer to “dsPIC30F Family Reference Manual” (DS70046) for ...
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... Interrupt on a 32-bit Period Register Match These operating modes are determined by setting the appropriate bit(s) in the 16-bit T2CON and T3CON SFRs. © 2006 Microchip Technology Inc. dsPIC30F6010 For 32-bit timer/counter operation, Timer2 is the least significant word and Timer3 is the most significant word of the 32-bit timer. Note: For 32-bit timer operation, T3CON control bits are ignored ...
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... FIGURE 10-1: 32-BIT TIMER2/3 BLOCK DIAGRAM Data Bus<15:0> TMR3HLD 16 Write TMR2 Read TMR2 16 Reset TMR3 MSB ADC Event Trigger Comparator x 32 Equal PR3 0 T3IF Event Flag 1 TGATE (T2CON<6>) T2CK Note: Timer Configuration bit T32, T2CON(<3>) must be set to ‘1’ for a 32-bit timer/counter operation. All control bits are respective to the T2CON register ...
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... Equal Comparator x 16 Reset 0 T3IF Event Flag 1 TGATE T3CK © 2006 Microchip Technology Inc. PR2 Comparator x 16 TMR2 Q D TGATE Gate Sync PR3 TMR3 Q D TGATE Q CK Sync dsPIC30F6010 Sync TCKPS<1:0> 2 TON Prescaler 1, 8, 64, 256 TCKPS<1:0> 2 TON Prescaler 1, 8, 64, 256 DS70119E-page 63 ...
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... Timer Gate Operation The 32-bit timer can be placed in the Gated Time Accu- mulation mode. This mode allows the internal T increment the respective timer when the gate input sig- nal (T2CK pin) is asserted high. Control bit TGATE (T2CON<6>) must be set to enable this mode. When in this mode, Timer2 is the originating clock source ...
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TABLE 10-1: TIMER2/3 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON — TSIDL — T3CON 0112 TON — TSIDL — ...
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... NOTES: DS70119E-page 66 © 2006 Microchip Technology Inc. ...
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... Note: Timer Configuration bit T32, T4CON(<3>) must be set to ‘ control bits are respective to the T4CON register. © 2006 Microchip Technology Inc. dsPIC30F6010 The Timer4/5 module is similar in operation to the Timer 2/3 module. However, there are some differences, which are listed below: • ...
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... FIGURE 11-2: 16-BIT TIMER4 BLOCK DIAGRAM (TYPE B TIMER) Equal Comparator x 16 Reset 0 T4IF Event Flag 1 TGATE T4CK FIGURE 11-3: 16-BIT TIMER5 BLOCK DIAGRAM (TYPE C TIMER) ADC Event Trigger Equal Reset 0 T5IF Event Flag 1 TGATE T5CK DS70119E-page 68 PR4 TMR4 Q D TGATE ...
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TABLE 11-1: TIMER4/5 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 TMR4 0114 TMR5HLD 0116 TMR5 0118 PR4 011A PR5 011C T4CON 011E TON — TSIDL — T5CON 0120 TON — TSIDL — Legend: u ...
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... NOTES: DS70119E-page 70 © 2006 Microchip Technology Inc. ...
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... Simple Capture Event mode • Timer2 and Timer3 mode selection • Interrupt on input capture event These operating modes are determined by setting the appropriate bits in the ICxCON register (where x = 1,2,...,N). The dsPIC30F6010 device has 8 capture channels. FIGURE 12-1: INPUT CAPTURE MODE BLOCK DIAGRAM ICx ...
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... CAPTURE BUFFER OPERATION Each capture channel has an associated FIFO buffer, which is four 16-bit words deep. There are two status flags, which provide status on the FIFO buffer: • ICBFNE – Input Capture Buffer Not Empty • ICOV – Input Capture Overflow ...
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TABLE 12-1: INPUT CAPTURE REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 IC1BUF 0140 IC1CON 0142 — — ICSIDL — IC2BUF 0144 IC2CON 0146 — — ICSIDL — IC3BUF 0148 IC3CON 014A — — ICSIDL ...
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... NOTES: DS70119E-page 74 © 2006 Microchip Technology Inc. ...
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... Interrupt on Output Compare/PWM Event These operating modes are determined by setting the appropriate bits in the 16-bit OCxCON SFR (where x = 1,2,3,...,N). The dsPIC30F6010 device has 8 compare channels. OCxRS and OCxR in the figure represent the Dual Compare registers. In the Dual Compare mode, the OCxR register is used for the first compare and OCxRS is used for the second compare ...
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... Timer2 and Timer3 Selection Mode Each output compare channel can select between one of two 16-bit timers; Timer2 or Timer3. The selection of the timers is controlled by the OCTSEL bit (OCxCON<3>). Timer2 is the default timer resource for the Output Compare module. 13.2 Simple Output Compare Match Mode When control bits OCM< ...
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... The IF bit is located in the IFS0 Status register, and must be cleared in software. The interrupt is enabled via the respective Timer Interrupt Enable bit (T2IE or T3IE), located in the IEC0 Control register. The output compare interrupt flag is never set during the PWM mode of operation. dsPIC30F6010 DS70119E-page 77 ...
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TABLE 13-1: OUTPUT COMPARE REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 OC1RS 0180 OC1R 0182 OC1CON 0184 — — OCSIDL — OC2RS 0186 OC2R 0188 OC2CON 018A — — OCSIDL — OC3RS ...
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... Figure 14-1 depicts the Quadrature Encoder Interface block diagram. TQCKPS<1:0> TQCS TQGATE CK Q 16-bit Up/Down Counter (POSCNT) 2 Quadrature Encoder Interface Logic Comparator/ Zero Detect 3 QEIM<2:0> Mode Select Max Count Register (MAXCNT) dsPIC30F6010 bits QEIM<2:0> (QEICON<10:8>). 2 Prescaler 1, 8, 64, 256 QEIIF Event Flag Reset Equal DS70119E-page 79 ...
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... Quadrature Encoder Interface Logic A typical incremental (a.k.a. optical) encoder has three outputs: Phase A, Phase B, and an index pulse. These signals are useful and often required in position and speed control of ACIM and SR motors. The two channels, Phase A (QEA) and Phase B (QEB), have a unique relationship ...
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... When UPDN = 1, the timer will count up. When UPDN = 0, the timer will count down. © 2006 Microchip Technology Inc. dsPIC30F6010 In addition, control bit UPDN_SRC (QEICON<0>) determines whether the timer count direction state is based on the logic state, written into the UPDN Control/ Status bit (QEICON< ...
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... TIMER OPERATION DURING CPU IDLE MODE When the CPU is placed in the Idle mode and the QEI module is configured in the 16-bit Timer mode, the 16-bit timer will operate if the (QEICON<13> This bit defaults to a logic ‘0’ upon executing POR and BOR. For halting the timer module during the CPU Idle mode, QEISIDL should be set to ‘ ...
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TABLE 14-1: QEI REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Name QEICON 0122 CNTERR — QEISIDL INDX UPDN QEIM2 QEIM1 QEIM0 SWPAB PCDOUT TQGATE TQCKPS1 TQCKPS0 POSRES TQCS UPDN_SRC 0000 0000 ...
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... NOTES: DS70119E-page 84 © 2006 Microchip Technology Inc. ...
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... Switched Reluctance (SR) Motor • Brushless DC (BLDC) Motor • Uninterruptible Power Supply (UPS) © 2006 Microchip Technology Inc. dsPIC30F6010 The PWM module has the following features: • 8 PWM I/O pins with 4 duty cycle generators • 16-bit resolution • ‘On-the-Fly’ PWM frequency changes • ...
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... FIGURE 15-1: PWM MODULE BLOCK DIAGRAM PWMCON1 PWMCON2 DTCON1 DTCON2 FLTACON FLTBCON OVDCON PTMR Comparator PTPER PTPER Buffer PTCON Comparator SEVTCMP PWM time base Note: Details of PWM Generator #1, #2, and #3 not shown for clarity. DS70119E-page 86 PWM Enable and Mode SFRs ...
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... The interrupt signals generated by the PWM time base depend on the mode selection bits (PTMOD<1:0>) and the postscaler bits (PTOPS<3:0>) in the PTCON SFR. © 2006 Microchip Technology Inc. dsPIC30F6010 15.1.1 FREE RUNNING MODE In the Free Running mode, the PWM time base counts upwards until the value in the Time Base Period regis- ter (PTPER) is matched ...
Page 90
... DOUBLE UPDATE MODE In the Double Update mode (PTMOD<1:0> = 11), an interrupt event is generated each time the PTMR regis- ter is equal to zero, as well as each time a period match occurs. The postscaler selection bits have no effect in this mode of the timer. The Double Update mode provides two additional func- tions to the user ...
Page 91
... Period/2 PTPER Duty Cycle 0 Period © 2006 Microchip Technology Inc. dsPIC30F6010 15.5 PWM Duty Cycle Comparison Units There are four 16-bit special function registers (PDC1, PDC2, PDC3 and PDC4) used to specify duty cycle values for the PWM module. The value in each duty cycle register determines the amount of time that the PWM output is in the active state ...
Page 92
... Complementary PWM Operation In the Complementary mode of operation, each pair of PWM outputs is obtained by a complementary PWM signal. A dead time may be optionally inserted during device switching, when both outputs are inactive for a short period (Refer to Section 15.7 “Dead-Time Gen- erators”). ...
Page 93
... PWM I/O pins are driven to the inactive state, the PTEN bit is cleared, and an interrupt is generated. © 2006 Microchip Technology Inc. dsPIC30F6010 Time selected by DTSxI bit ( 15.10 PWM Output Override The PWM output override bits allow the user to manu- ally drive the PWM I/O pins to specified logic states, independent of the duty cycle comparison units ...
Page 94
... PWM Output and Polarity Control There are three device Configuration bits associated with the PWM module that provide PWM output pin control: • HPOL Configuration bit • LPOL Configuration bit • PWMPIN Configuration bit These three bits in the FPORBOR configuration regis- ter (see Section 21) work in conjunction with the four PWM Enable bits (PWMEN< ...
Page 95
... PWM time base. The SEVTDIR control bit has no effect unless the PWM time base is configured for an Up/Down Counting mode. © 2006 Microchip Technology Inc. dsPIC30F6010 15.14.1 SPECIAL EVENT TRIGGER POSTSCALER The PWM special event trigger has a postscaler that allows a 1:1 to 1:16 postscale ratio. The postscaler is configured by writing the SEVOPS< ...
Page 96
TABLE 15-2: 8-OUTPUT PWM REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 PTCON 01C0 PTEN — PTSIDL — PTMR 01C2 PTDIR PTPER 01C4 — SEVTCMP 01C6 SEVTDIR PWMCON1 01C8 — — — — PTMOD4 PTMOD3 ...
Page 97
... SCL transitions while SPIROV is 1, effectively disabling the module until SPIxBUF is read by user software. © 2006 Microchip Technology Inc. dsPIC30F6010 Transmit writes are also double-buffered. The user writes to SPIxBUF. When the master or slave transfer is completed, the contents of the shift register (SPIxSR) is moved to the receive buffer ...
Page 98
... FIGURE 16-1: SPI BLOCK DIAGRAM Read SPIxBUF Receive SDIx bit 0 SDOx SS & FSYNC Control SSx SCKx Note FIGURE 16-2: SPI MASTER/SLAVE CONNECTION SPI Master Serial Input Buffer (SPIxBUF) Shift Register (SPIxSR) MSb PROCESSOR 1 Note DS70119E-page 96 Internal Data Bus Write SPIxBUF ...
Page 99
... Therefore, when the SSx pin is asserted low again, transmission/reception will begin at the MSb, even if SSx had been deasserted in the middle of a transmit/receive. © 2006 Microchip Technology Inc. dsPIC30F6010 16.4 SPI Operation During CPU Sleep Mode During Sleep mode, the SPI module is shut-down. If ...
Page 100
TABLE 16-1: SPI1 REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name SPI1STAT 0220 SPIEN — SPISIDL — SPI1CON 0222 — FRMEN SPIFSD — DISSDO MODE16 SPI1BUF 0224 Legend uninitialized bit Note: ...
Page 101
... I2CRCV and an interrupt pulse is generated. During transmis- sion, the I2CTRN is not double-buffered. Note: Following a Restart condition in 10-bit mode, the user only needs to match the first 7-bit address. dsPIC30F6010 2 C port can Standard and Fast mode specifica bus. ...
Page 102
... FIGURE 17-2: I C™ BLOCK DIAGRAM Shift SCL Clock SDA Match Detect Stop bit Detect Start, Restart, Stop bit Generate Acknowledge Shift Clock DS70119E-page 100 I2CRCV I2CRSR LSB Addr_Match I2CADD Start and Collision Detect Generation Clock Stretching I2CTRN LSB Reload ...
Page 103
... ACK received from the master. © 2006 Microchip Technology Inc. dsPIC30F6010 17.3.2 SLAVE RECEPTION If the R_W bit received is a ‘0’ during an address match, Receive mode is initiated. Incoming bits are sampled on the rising edge of SCL ...
Page 104
... MODE SLAVE RECEPTION Once addressed, the master can generate a Repeated Start, reset the high byte of the address and set the R_W bit without generating a Stop bit, thus initiating a slave transmit operation. 17.5 Automatic Clock Stretch In the slave modes, the module can synchronize buffer reads and write to the master device by clock stretching ...
Page 105
... BRG is reloaded when the SCL pin is sampled high per the I C standard, FSCK may be 100 kHz or 400 kHz. However, the user can specify any baud rate MHz. I2CBRG values are illegal. dsPIC30F6010 2 C bus will 2 C DS70119E-page 103 ...
Page 106
... EQUATION 17-1: SERIAL CLOCK RATE ⎛ ------------ - -------------------------- - I2CBRG = – ⎝ 111 111 SCL 17.12.4 CLOCK ARBITRATION Clock arbitration occurs when the master deasserts the SCL pin (SCL allowed to float high) during any receive, transmit, or Restart/Stop condition. When the SCL pin is allowed to float high, the Baud Rate Generator is suspended from counting until the SCL pin is actually sampled high ...
Page 107
TABLE 17- REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 — — — — I2CRCV 0200 — — — — I2CTRN 0202 — — — — I2CBRG 0204 — I2CCON 0206 I2CEN ...
Page 108
... NOTES: DS70119E-page 106 © 2006 Microchip Technology Inc. ...
Page 109
... Load TSR Transmit Shift Register (UxTSR) ‘0’ (Start) ‘1’ (Stop) Parity 16 Divider Generator Control Signals dsPIC30F6010 Control and Status bits Transmit Control – Control TSR – Control Buffer – Generate Flags – Generate Interrupt UxTXIF 16X Baud Clock from Baud Rate ...
Page 110
... FIGURE 18-2: UART RECEIVER BLOCK DIAGRAM LPBACK From UxTX 1 UxRX 0 · Start bit Detect · Parity Check · Stop bit Detect · Shift Clock Generation · Wake Logic DS70119E-page 108 Internal Data Bus 16 Read Write UxRXREG Low Byte URX8 Receive Buffer Control – ...
Page 111
... The STSEL bit determines whether one or two Stop bits will be used during data transmission. The default (Power-on) setting of the UART is 8 bits, no parity, 1 Stop bit (typically represented 1). © 2006 Microchip Technology Inc. dsPIC30F6010 18.3 Transmitting Data 18.3.1 TRANSMITTING IN 8-BIT DATA MODE ...
Page 112
... TRANSMIT INTERRUPT The transmit interrupt flag (U1TXIF or U2TXIF) is located in the corresponding interrupt flag register. The transmitter generates an edge to set the UxTXIF bit. The condition for generating the interrupt depends on UTXISEL control bit UTXISEL = 0, an interrupt is generated when a word is transferred from the Transmit buffer to the Transmit Shift register (UxTSR) ...
Page 113
... Microchip Technology Inc. dsPIC30F6010 18.7 Loopback Mode Setting the LPBACK bit enables this special mode in which the UxTX pin is internally connected to the UxRX pin ...
Page 114
... UART Operation During CPU Sleep and Idle Modes 18.10.1 UART OPERATION DURING CPU SLEEP MODE When the device enters Sleep mode, all clock sources to the module are shutdown and stay at logic ‘0’. If entry into Sleep mode occurs while a transmission is in progress, then the transmission is aborted. The UxTX pin is driven to logic ‘ ...
Page 115
TABLE 18-1: UART1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 U1MODE 020C UARTEN — USIDL — U1STA 020E UTXISEL — — — UTXBRK UTXEN U1TXREG 0210 — — — — U1RXREG 0212 ...
Page 116
... NOTES: DS70119E-page 114 © 2006 Microchip Technology Inc. ...
Page 117
... The Controller Area Network (CAN) module is a serial interface, useful for communicating with other CAN modules or microcontroller devices. This interface/ protocol was designed to allow communications within noisy environments. The dsPIC30F6010 has 2 CAN modules. The CAN module is a communication controller imple- menting the CAN 2.0 A/B protocol, as defined in the BOSCH specification ...
Page 118
... FIGURE 19-1: CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM BUFFERS TXB0 TXB1 Message Queue Control Transmit Byte Sequencer PROTOCOL ENGINE Transmit Logic (1) CiTX Note refers to a particular CAN module (CAN1 or CAN2). DS70119E-page 116 Acceptance Mask TXB2 RXM0 A Acceptance Filter c RXF0 ...
Page 119
... CPU interface. 19.3.6 LOOP BACK MODE If the Loopback mode is activated, the module will con- nect the internal transmit signal to the internal receive signal at the module boundary. The transmit and receive pins revert to their Port I/O function. dsPIC30F6010 mode is selected when DS70119E-page 117 ...
Page 120
... Message Reception 19.4.1 RECEIVE BUFFERS The CAN bus module has 3 receive buffers. However, one of the receive buffers is always committed to mon- itoring the bus for incoming messages. This buffer is called the message assembly buffer (MAB). So there are 2 receive buffers visible, RXB0 and RXB1, that can ...
Page 121
... TXERR (CiTXnCON<4>) flag automatically cleared. © 2006 Microchip Technology Inc. dsPIC30F6010 Setting TXREQ bit simply flags a message buffer as enqueued for transmission. When the module detects an available bus, it begins transmitting the message which has been determined to have the highest priority. If the transmission completes successfully on the first attempt, the TXREQ bit is cleared automatically and an interrupt is generated if TXIE was set ...
Page 122
... TRANSMIT INTERRUPTS Transmit interrupts can be divided into 2 major groups, each including various conditions that generate interrupts: • Transmit Interrupt At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message for transmission. Reading the TXnIF flags will indicate which transmit buffer is available and caused the interrupt ...
Page 123
... SJW<1:0> bits (CiCFG1<7:6>). The value of the syn- chronization jump width will be added to Phase1 Seg or subtracted from Phase2 Seg. The re-synchronization jump width is programmable between 1 T The following requirement must be fulfilled while setting the SJW<1:0> bits: • Phase2 Seg > Synchronization Jump Width dsPIC30F6010 , it is possible to Q /2. The Q and ...
Page 124
TABLE 19-1: CAN1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 — — — C1RXF0SID 0300 C1RXF0EIDH 0302 — — — — C1RXF0EIDL 0304 Receive Acceptance Filter 0 Extended Identifier <5:0> — — — C1RXF1SID ...
Page 125
TABLE 19-1: CAN1 REGISTER MAP (CONTINUED) SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 C1TX1B1 0356 Transmit Buffer 1 Byte 1 C1TX1B2 0358 Transmit Buffer 1 Byte 3 C1TX1B3 035A Transmit Buffer 1 Byte 5 C1TX1B4 035C ...
Page 126
TABLE 19-2: CAN2 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 — — — C2RXF0SID 03C0 C2RXF0EIDH 03C2 — — — — C2RXF0EIDL 03C4 Receive Acceptance Filter 0 Extended Identifier <5:0> — — — C2RXF1SID ...
Page 127
TABLE 19-2: CAN2 REGISTER MAP (CONTINUED) SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 C2TX1B4 041C Transmit Buffer 1 Byte 7 C2TX1CON 041E — — — — C2TX0SID 0420 Transmit Buffer 0 Standard Identifier <10:6> C2TX0EID 0422 ...
Page 128
... NOTES: DS70119E-page 126 © 2006 Microchip Technology Inc. ...
Page 129
... REF REF being able to operate while the device is in Sleep mode. © 2006 Microchip Technology Inc. dsPIC30F6010 The ADC module has six 16-bit registers: • ADC Control Register1 (ADCON1) • ADC Control Register2 (ADCON2) • ADC Control Register3 (ADCON3) • ADC Input Select Register (ADCHS) • ...
Page 130
... FIGURE 20-1: 10-BIT HIGH-SPEED ADC FUNCTIONAL BLOCK DIAGRAM V + REF V - REF AN0 AN0 AN3 AN6 AN9 AN1 AN1 AN4 AN7 AN10 AN2 AN2 AN5 AN8 AN11 AN0 AN1 AN2 AN3 AN3 AN4 AN4 AN5 AN5 AN6 AN6 AN7 AN7 AN8 AN8 ...
Page 131
... ADCSSL register is ‘1’, the corre- sponding input is selected. The inputs are always scanned from lower to higher numbered inputs, starting after each interrupt. If the number of inputs selected is greater than the number of samples taken per interrupt, the higher numbered inputs are unused. dsPIC30F6010 DS70119E-page 129 ...
Page 132
... Programming the Start of Conversion Trigger The conversion trigger will terminate acquisition and start the requested conversions. The SSRC<2:0> bits select the source of the conversion trigger. The SSRC bits provide for alternate sources of conversion trigger. When SSRC<2:0> = 000, the conversion trigger is under software control ...
Page 133
... See Figure 20-2 for recommended dsPIC30F6010 A/D Channels Configuration REF REF CH1, CH2 or CH3 ANx S/H ADC ...
Page 134
... The ADC converts the value held on one S/H channel, while the second S/H channel acquires a new input sample. DS70119E-page 132 The following figure depicts the recommended circuit for the conversion rates above 500 ksps dsPIC30F6010 20.7.1.2 Multiple Analog Inputs The ADC can also be used to sample multiple analog inputs using multiple sample and hold channels ...
Page 135
... ADCS<5:0> control bits in the ADCON3 register by AD • Configure the sampling time ing: SAMC<4:0> = 00010 Select at least two channels per analog input pin by writing to the ADCHS register dsPIC30F6010 + and V - pins following REF REF 1 = 138. writ- AD DS70119E-page 133 ...
Page 136
... ADC Acquisition Requirements The analog input model of the 10-bit ADC is shown in Figure 20-3. The total sampling time for the ADC is a function of the internal amplifier settling time, device V and the holding capac- DD itor charge time. For the ADC to meet its specified accuracy, the ...
Page 137
... Each of the output formats translates to a 16-bit result on the data bus. Write data will always be in right justified (integer) format. d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 dsPIC30F6010 ...
Page 138
... Configuring Analog Port Pins The use of the ADPCFG and TRIS registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their correspond- ing TRIS bit set (input). If the TRIS bit is cleared (out- ...
Page 139
TABLE 20-2: ADC REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 ADCBUF0 0280 — — — — ADCBUF1 0282 — — — — ADCBUF2 0284 — — — — ADCBUF3 0286 — — — — ...
Page 140
... NOTES: DS70119E-page 138 © 2006 Microchip Technology Inc. ...
Page 141
... In the Idle mode, the clock sources are still active, but the CPU is shut-off. The RC oscillator option saves system cost, while the LP crystal option saves power. © 2006 Microchip Technology Inc. dsPIC30F6010 21.1 Oscillator System Overview The dsPIC30F oscillator system has the following modules and features: • ...
Page 142
... TABLE 21-1: OSCILLATOR OPERATING MODES Oscillator Mode XTL 200 kHz-4 MHz crystal on OSC1:OSC2 MHz-10 MHz crystal on OSC1:OSC2 PLL 4x 4 MHz-10 MHz crystal on OSC1:OSC2. 4x PLL enabled PLL 8x 4 MHz-10 MHz crystal on OSC1:OSC2. 8x PLL enabled PLL 16x 4 MHz-10 MHz crystal on OSC1:OSC2. 16x PLL enabled ...
Page 143
... FIGURE 21-1: OSCILLATOR SYSTEM BLOCK DIAGRAM OSC1 Primary Oscillator OSC2 POR Done SOSCO 32 kHz LP Oscillator SOSCI © 2006 Microchip Technology Inc. dsPIC30F6010 F PLL PLL x4, x8, x16 PLL Lock Primary Osc Primary Oscillator Stability Detector Oscillator Start-up Clock Timer Switching and Control ...
Page 144
... Oscillator Configurations 21.2.1 INITIAL CLOCK SOURCE SELECTION While coming out of Power-on Reset or Brown-out Reset, the device selects its clock source based on: a) FOS<1:0> Configuration bits that select one of four oscillator groups. b) AND FPR<3:0> Configuration bits that select one of 13 oscillator choices within the primary group ...
Page 145
... Reset address into the oscillator fail trap vector. In this event, the CF (Clock Fail) status bit (OSCCON<3>) is also set whenever a clock failure is recognized. In the event of a clock failure, the WDT is unaffected and continues to run on the LPRC clock. dsPIC30F6010 FRC Frequency - 10.5% - 12.0% Oscillator ...
Page 146
... If the oscillator has a very slow start-up time coming out of POR, BOR or Sleep possible that the PWRT timer will expire before the oscillator has started. In such cases, the FSCM will be activated and the FSCM will initiate a clock failure trap, and the COSC< ...
Page 147
... The total delay is at device power-up T have expired, SYSRST will be negated on the next leading edge of the Q1 clock, and the PC will jump to the Reset vector. The timing for the SYSRST signal is shown in Figure 21-3 through Figure 21-5. dsPIC30F6010 SYSRST , which is POR ) is applied ...
Page 148
... FIGURE 21-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED MCLR INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset FIGURE 21-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset FIGURE 21-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO V ...
Page 149
... The BOR voltage trip points indicated here are nominal values provided for design guidance only. © 2006 Microchip Technology Inc. dsPIC30F6010 A BOR will generate a Reset pulse which will reset the device. The BOR will select the clock source, based on the device Configuration bit values (FOS<1:0> and FPR< ...
Page 150
... Table 21-5 shows the Reset conditions for the RCON Register. Since the control bits within the RCON regis- ter are R/W, the information in the table implies that all the bits are negated prior to the action specified in the condition column. TABLE 21-5: ...
Page 151
... LP is the oscillator used on wake-up, then the start-up delay will be equal to T timer delay are not applied. In order to have the small- est possible start-up delay when waking up from Sleep, one of these faster wake-up options should be selected before entering Sleep. dsPIC30F6010 , T and T delays are POR LOCK PWRT (~ applied ...
Page 152
... Any interrupt that is individually enabled (using the corresponding IE bit) and meets the prevailing priority level will be able to wake-up the processor. The proces- sor will process the interrupt and branch to the ISR. The Sleep status bit in RCON register is set upon wake-up. ...
Page 153
... These pin pairs are named EMUD/EMUC, EMUD1/ EMUC1, EMUD2/EMUC2 and EMUD3/EMUC3. © 2006 Microchip Technology Inc. dsPIC30F6010 In each case, the selected EMUD pin is the Emulation/ Debug Data line, and the EMUC pin is the Emulation/ Debug Clock line. These pins will interface to the MPLAB ICD 2 module available from Microchip ...
Page 154
TABLE 21-7: SYSTEM INTEGRATION REGISTER MAP SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name . RCON 0740 TRAPR IOPUWR BGST LVDEN OSCCON 0742 — — COSC<1:0> — PMD1 0770 T5MD T4MD T3MD T2MD T1MD QEIMD ...
Page 155
... MPLAB PM3 Device Programmer - PICkit™ 2 Development Programmer • Low-Cost Demonstration and Development Boards and Evaluation Kits © 2006 Microchip Technology Inc. dsPIC30F6010 22.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market ...
Page 156
... MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging ...
Page 157
... Microchip Technology Inc. dsPIC30F6010 22.9 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD powerful, low-cost, ...
Page 158
... PICSTART Plus Development Programmer The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages pins. ...
Page 159
... All instructions are a single word, except for certain double-word instructions, which were made double- word instructions so that all the required information is available in these 48 bits. In the second word, the 8 MSb’s are ‘0’s. If this second word is executed as an instruction (by itself), it will execute as a NOP. dsPIC30F6010 DS70119E-page 157 ...
Page 160
... Most single word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruc- tion. In these cases, the execution takes two instruction cycles with the additional instruction cycle(s) executed as a NOP. Notable exceptions are the BRA (uncondi- ...
Page 161
... Wy {[W10]+=6, [W10]+=4, [W10]+=2, [W10], [W10]-=6, [W10]-=4, [W10]-=2, [W11]+=6, [W11]+=4, [W11]+=2, [W11], [W11]-=6, [W11]-=4, [W11]-=2, [W11+W12], none} Y data space prefetch destination register for DSP instructions Wyd © 2006 Microchip Technology Inc. dsPIC30F6010 Description {W0..W15} { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] } {W0..W15} {W0..W15} {W0..W15} { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] } {W4 ...
Page 162
... TABLE 23-2: INSTRUCTION SET OVERVIEW Base Assembly Instr Assembly Syntax Mnemonic # 1 ADD ADD Acc ADD f ADD f,WREG ADD #lit10,Wn ADD Wb,Ws,Wd ADD Wb,#lit5,Wd ADD Wso,#Slit4,Acc 2 ADDC ADDC f ADDC f,WREG ADDC #lit10,Wn ADDC Wb,Ws,Wd ADDC Wb,#lit5,Wd 3 AND AND f AND f,WREG ...
Page 163
... DAW DAW Wn 26 DEC DEC f DEC f,WREG DEC Ws,Wd © 2006 Microchip Technology Inc. dsPIC30F6010 # of Description words Bit Toggle f Bit Toggle Ws Bit Test f, Skip if Clear Bit Test Ws, Skip if Clear Bit Test f, Skip if Set Bit Test Ws, Skip if Set Bit Test f Bit Test Bit Test Bit Test Ws< ...
Page 164
... TABLE 23-2: INSTRUCTION SET OVERVIEW Base Assembly Instr Assembly Syntax Mnemonic # 27 DEC2 DEC2 f DEC2 f,WREG DEC2 Ws,Wd 28 DISI DISI #lit14 29 DIV DIV.S Wm,Wn DIV.SD Wm,Wn DIV.U Wm,Wn DIV.UD Wm,Wn 30 DIVF DIVF Wm, #lit14,Expr DO Wn,Expr Wm*Wm,Acc,Wx,Wy,Wxd 33 EDAC EDAC Wm*Wm,Acc,Wx,Wy,Wxd 34 EXCH EXCH Wns,Wnd ...
Page 165
... RESET RESET 60 RETFIE RETFIE 61 RETLW RETLW #lit10,Wn 62 RETURN RETURN © 2006 Microchip Technology Inc. dsPIC30F6010 # of Description words Move Move Move f to WREG Move 16-bit literal to Wn Move 8-bit literal to Wn Move Move Move WREG to f Move Double from W(ns):W(ns+ Move Double from Ws to W(nd+1):W(nd) ...
Page 166
... TABLE 23-2: INSTRUCTION SET OVERVIEW Base Assembly Instr Assembly Syntax Mnemonic # 63 RLC RLC f RLC f,WREG RLC Ws,Wd 64 RLNC RLNC f RLNC f,WREG RLNC Ws,Wd 65 RRC RRC f RRC f,WREG RRC Ws,Wd 66 RRNC RRNC f RRNC f,WREG RRNC Ws,Wd 67 SAC SAC Acc,#Slit4,Wdo SAC.R ...
Page 167
... XOR XOR f XOR f,WREG XOR #lit10,Wn XOR Wb,Ws,Wd XOR Wb,#lit5, Ws,Wnd © 2006 Microchip Technology Inc. dsPIC30F6010 # of Description words Write Ws to Prog<15:0> Unlink frame pointer .XOR. WREG WREG = f .XOR. WREG Wd = lit10 .XOR .XOR .XOR. lit5 Wnd = Zero-Extend Status Flags cycle Affected ...
Page 168
... NOTES: DS70119E-page 166 © 2006 Microchip Technology Inc. ...
Page 169
... Microchip Technology Inc. (except V and MCLR) (Note 1) .................................... -0. .......................................................................................................... ± > ...................................................................................................± the MCLR/V pin, inducing currents greater than 80 mA, may cause latchup Max MIPS dsPIC30F6010-30I dsPIC30F6010-20I 30 — 15 — 7.5 dsPIC30F6010 + 0.3V) DD pin, rather PP dsPIC30F6010-20E 20 — — — — 10 7.5 — DS70119E-page 167 ...
Page 170
... TABLE 24-2: THERMAL OPERATING CONDITIONS Rating dsPIC30F6010-30I Operating Junction Temperature Range Operating Ambient Temperature Range dsPIC30F6010-20I Operating Junction Temperature Range Operating Ambient Temperature Range dsPIC30F6010-20E Operating Junction Temperature Range Operating Ambient Temperature Range Power Dissipation: Internal chip power dissipation: ∑ – ...
Page 171
... All I/O pins are configured as Inputs and pulled to V MCLR = V , WDT, FSCM, LVD and BOR are disabled. CPU, SRAM, Program Memory and Data DD Memory are operational. No peripheral modules are operating. © 2006 Microchip Technology Inc. dsPIC30F6010 ) DD Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40° ...
Page 172
... TABLE 24-6: DC CHARACTERISTICS: IDLE CURRENT (I DC CHARACTERISTICS Parameter (1,2) Typical Max No. Operating Current ( DC51a 6.7 10 DC51b 6.3 10 DC51c 6.1 10 DC51e 13 18 DC51f 13 18 DC51g 13 18 DC50a 11 15 DC50b 10 15 DC50c 10 15 DC50e 23 35 DC50f 21 35 DC50g 21 35 DC43a 17 26 DC43b ...
Page 173
... LVD, BOR, WDT, etc. are all switched off. 3: The current is the additional current consumed when the module is enabled. This current should be added to the base I current. PD © 2006 Microchip Technology Inc. dsPIC30F6010 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40° -40°C T ...
Page 174
... TABLE 24-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS DC CHARACTERISTICS Param Symbol Characteristic No Input Low-Voltage DI10 I/O pins: with Schmitt Trigger buffer DI15 MCLR DI16 OSC1 (in XT, HS and LP modes) DI17 OSC1 (in RC mode) DI18 SDA, SCL DI19 SDA, SCL V Input High Voltage ...
Page 175
... TBD (2) V – 0.7 — — DD TBD — — V – 0.7 — — DD TBD — — — — 15 — — 50 — — 400 dsPIC30F6010 +85°C for Industrial A T +125°C for Extended A Units Conditions 8.5 mA 2.0 mA 1.6 mA 2.0 mA ...
Page 176
... TABLE 24-10: ELECTRICAL CHARACTERISTICS: LVDL DC CHARACTERISTICS Param Symbol Characteristic No. LV10 V LVDL Voltage on V PLVD transition high to low LV15 V External LVD input pin LVDIN threshold voltage Note 1: These parameters are characterized but not tested in manufacturing. 2: These values not in usable operating range. ...
Page 177
... V — 5.5 MIN 4.5 — 5.5 3.0 — 5.5 — 2 — 40 100 — — 4 — — — dsPIC30F6010 T +85°C for Industrial A +125°C for Extended A Max Units Conditions — V Not in operating range 2.71 V 4.4 V 4.73 V — +85°C for Industrial A T +125°C for Extended ...
Page 178
... AC Characteristics and Timing Parameters The information contained in this section defines dsPIC30F AC characteristics and timing parameters. TABLE 24-13: TEMPERATURE AND VOLTAGE SPECIFICATIONS – CHARACTERISTICS FIGURE 24-3: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 - for all pins except OSC2 Pin ...
Page 179
... T — OSC — — — 6 — equals four times the input oscillator time-base period. All specified values ) and high for the Q3-Q4 period (1 dsPIC30F6010 -40°C T +85°C for Industrial A -40°C T +125°C for Extended A Units Conditions 40 MHz EC 10 MHz ...
Page 180
... TABLE 24-15: PLL CLOCK TIMING SPECIFICATIONS (V AC CHARACTERISTICS Param Symbol Characteristic No. OS50 F PLL Input Frequency Range PLLI OS51 F On-Chip PLL Output SYS OS52 T PLL Start-up Time (Lock Time) LOC Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested ...
Page 181
... Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C -40°C T Min Typ Max Units -35 — +35 % changes. DD dsPIC30F6010 (3) (3) (3) MIPS MIPS w PLL x8 w PLL x16 — — 8.0 16.0 20.0 — — — 8.0 16.0 20.0 — ...
Page 182
... FIGURE 24-5: CLKO AND I/O TIMING CHARACTERISTICS I/O Pin (Input) I/O Pin Old Value (Output) Note: Refer to Figure 24-3 for load conditions. TABLE 24-20: CLKO AND I/O TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. DO31 T R Port output rise time IO DO32 ...
Page 183
... TIMER TIMING CHARACTERISTICS V DD SY12 MCLR Internal POR SY11 PWRT Time-out SY30 OSC Time-out Internal Reset Watchdog Timer Reset I/O Pins SY35 FSCM Delay Note: Refer to Figure 24-3 for load conditions. © 2006 Microchip Technology Inc. dsPIC30F6010 SY10 SY20 SY13 SY13 DS70119E-page 181 ...
Page 184
... TABLE 24-21: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. SY10 TmcL MCLR Pulse Width (low) SY11 T Power-up Timer Period PWRT SY12 T Power On Reset Delay POR SY13 T I/O High-impedance from MCLR ...
Page 185
... TCS (T1CON, bit 1)) TA20 T Delay from External TxCK Clock CKEXTMRL Edge to Timer Increment Note: Timer1 is a Type A. © 2006 Microchip Technology Inc. dsPIC30F6010 Tx11 Tx10 Tx15 OS60 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C -40°C T ...
Page 186
... TABLE 24-24: TIMER2 AND TIMER4 EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. TtxH TB10 TxCK High Time TB11 TtxL TxCK Low Time TB15 TtxP TxCK Input Period Synchronous, TB20 T - Delay from External TxCK Clock CKEXT Edge to Timer Increment MRL ...
Page 187
... TQ20 T Delay from External TxCK Clock CKEXTMRL Edge to Timer Increment Note 1: These parameters are characterized but not tested in manufacturing. © 2006 Microchip Technology Inc. dsPIC30F6010 TQ10 TQ11 TQ15 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C T -40°C T ...
Page 188
... FIGURE 24-10: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS IC X Note: Refer to Figure 24-3 for load conditions. TABLE 24-27: INPUT CAPTURE TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. IC10 TccL ICx Input Low Time IC11 TccH ICx Input High Time IC15 TccP ICx Input Period Note 1: These parameters are characterized but not tested in manufacturing ...
Page 189
... Microchip Technology Inc. OC20 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) (2) Min Typ Max Units — — — — ns dsPIC30F6010 -40°C T +85°C for Industrial A -40°C T +125°C for Extended A Conditions — OC15 — OC20 DS70119E-page 187 ...
Page 190
... FIGURE 24-13: MOTOR CONTROL PWM MODULE FAULT TIMING CHARACTERISTICS FLTA/B MP20 PWMx FIGURE 24-14: MOTOR CONTROL PWM MODULE TIMING CHARACTERISTICS PWMx Note: Refer to Figure 24-3 for load conditions. TABLE 24-30: MOTOR CONTROL PWM MODULE TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No ...
Page 191
... T -40°C (1) (2) Typ Max 6 T — — — — — — CY dsPIC30F6010 +85°C for Industrial A T +125°C for Extended A Units Conditions ns — ns — ns — ns — 16, 32, 64, 128 and 256 (Note 16, 32, 64, 128 and 256 (Note 2) DS70119E-page 189 ...
Page 192
... FIGURE 24-16: QEI MODULE INDEX PULSE TIMING CHARACTERISTICS QEA (input) QEB (input) Ungated Index TQ51 Index Internal Position Counter Reset TABLE 24-32: QEI INDEX PULSE TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. TQ50 TqIL Filter Time to Recognize Low, with Digital Filter ...
Page 193
... Data Input 20 — X Data Input 20 — X dsPIC30F6010 SP20 SP21 LSb LSb IN -40°C T +85°C for Industrial A -40°C T +125°C for Extended A Max Units Conditions — ns — — ns — — ...
Page 194
... FIGURE 24-18: SPI MODULE MASTER MODE (CKE =1) TIMING CHARACTERISTICS SP36 SCK X (CKP = 0) SP11 SCK X (CKP = 1) SDO MSb X SP40 SP30,SP31 SDI X MSb IN SP41 TABLE 24-34: SPI MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. SP10 TscL SCK output low time ...
Page 195
... Data Input 20 — X Data Input 20 — SCK Input 120 — X Output 10 — (3) 1.5 T — CY +40 dsPIC30F6010 SP52 LSb SP51 LSb IN -40°C T +85°C for Industrial A -40°C T +125°C for Extended A Max Units Conditions — ns — — ns — — ...
Page 196
... FIGURE 24-20: SPI MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS SP60 SS X SP50 SCK X (CKP = 0) SP71 SCK X (CKP = 1) MSb SDO X SDI SDI X MSb IN SP41 SP40 Note: Refer to Figure 24-3 for load conditions. DS70119E-page 194 SP70 SP73 SP35 SP72 SP52 BIT14 - - - - - -1 LSb ...
Page 197
... Data Input 20 — X Data Input 20 — SCK input 120 — — (4) Edge 1 — — — dsPIC30F6010 -40°C T +85°C for Industrial A -40°C T +125°C for Extended A Max Units Conditions — ns — — ns — — — — ns See parameter D032 — ...
Page 198
... FIGURE 24-21: I C™ BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCL IM31 IM30 SDA Start Condition Note: Refer to Figure 24-3 for load conditions. 2 FIGURE 24-22: I C™ BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 SCL IM11 IM10 SDA In IM40 ...
Page 199
... MHz mode — 100 kHz mode 4.7 400 kHz mode 1.3 (2) 1 MHz mode TBD — 2 C™ pins (for 1 MHz mode only). dsPIC30F6010 -40°C T +85°C for Industrial A -40°C T +125°C for Extended A Max Units Conditions — s — ...
Page 200
... FIGURE 24-23: I C™ BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCL IS31 IS30 SDA Start Condition 2 FIGURE 24-24: I C™ BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 SCL IS30 IS31 SDA In IS40 SDA Out 2 TABLE 24-38: I C™ BUS DATA TIMING REQUIREMENTS (SLAVE MODE) ...