LPC2103FHN48,551 NXP Semiconductors, LPC2103FHN48,551 Datasheet - Page 8
![IC ARM7 MCU FLASH 32K 48-HVQFN](/photos/6/92/69297/48-hvqfn_sot778-3_pkg_sml.jpg)
LPC2103FHN48,551
Manufacturer Part Number
LPC2103FHN48,551
Description
IC ARM7 MCU FLASH 32K 48-HVQFN
Manufacturer
NXP Semiconductors
Series
LPC2100r
Datasheet
1.LPC2102FHN48551.pdf
(37 pages)
Specifications of LPC2103FHN48,551
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
Core Processor
ARM7
Core Size
16/32-Bit
Speed
70MHz
Connectivity
I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
32
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC21
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
8 KB
Interface Type
I2C/JTAG/SPI/SSP/UART
Maximum Clock Frequency
70 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, DB-LQFP48-LPC2103, MCB2103, MCB2103U, MCB2103UME, KSK-LPC2103-01, KSK-LPC2103-01PL, KSK-LPC2103-02
Development Tools By Supplier
OM10079, OM10081, OM10090
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Package
48HVQFN EP
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
70 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
568-4310 - EVAL BOARD LPC2158 W/LCD568-4302 - BOARD EVAL LPC210X KS2103 JLINK568-4301 - BOARD EVAL LPC210X KS2103568-4300 - BOARD EVAL LPC210X MCB2103568-4297 - BOARD EVAL LPC21XX MCB2100MCB2103UME - BOARD EVAL MCB2103 + ULINK-MEMCB2103U - BOARD EVAL MCB2103 + ULINK2MCB2103 - BOARD EVAL NXP LPC2101/2101/2103622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4690
935287391551
LPC2103FHN48-S
935287391551
LPC2103FHN48-S
NXP Semiconductors
Table 3.
LPC2101_02_03_4
Product data sheet
Symbol
P0.22/AD0.0
P0.23/AD0.1
P0.24/AD0.2
P0.25/AD0.6
P0.26/AD0.7
P0.27/TRST/
CAP2.0
P0.28/TMS/
CAP2.1
P0.29/TCK/
CAP2.2
P0.30/TDI/
MAT3.3
P0.31/TDO
RTCX1
RTCX2
RTCK
XTAL1
XTAL2
DBGSEL
RST
Pin description
Pin
32
33
34
38
39
8
9
10
15
16
20
25
26
11
12
27
6
[1]
[1]
[3]
[3]
[3]
[3]
[3]
[1]
[1]
[1]
[7][8]
[7][8]
[7]
…continued
Type
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I
I/O
I
I
I/O
I
I
I/O
I
O
O
O
I
O
I/O
I
O
I
I
Description
P0.22 — General purpose input/output digital pin.
AD0.0 — ADC 0, input 0.
P0.23 — General purpose input/output digital pin.
AD0.1 — ADC 0, input 1.
P0.24 — General purpose input/output digital pin.
AD0.2 — ADC 0, input 2.
P0.25 — General purpose input/output digital pin.
AD0.6 — ADC 0, input 6.
P0.26 — General purpose input/output digital pin.
AD0.7 — ADC 0, input 7.
P0.27 — General purpose input/output digital pin.
TRST — Test Reset for JTAG interface. If DBGSEL is HIGH, this pin is
automatically configured for use with EmbeddedICE (Debug mode).
CAP2.0 — Capture input for Timer 2, channel 0.
P0.28 — General purpose input/output digital pin.
TMS — Test Mode Select for JTAG interface. If DBGSEL is HIGH, this pin is
automatically configured for use with EmbeddedICE (Debug mode).
CAP2.1 — Capture input for Timer 2, channel 1.
P0.29 — General purpose input/output digital pin.
TCK — Test Clock for JTAG interface. This clock must be slower than
CPU clock (CCLK) for the JTAG interface to operate. If DBGSEL is HIGH, this
pin is automatically configured for use with EmbeddedICE (Debug mode).
CAP2.2 — Capture input for Timer 2, channel 2.
P0.30 — General purpose input/output digital pin.
TDI — Test Data In for JTAG interface. If DBGSEL is HIGH, this pin is
automatically configured for use with EmbeddedICE (Debug mode).
MAT3.3 — PWM output 3 for Timer 3.
P0.31 — General purpose output only digital pin.
TDO — Test Data Out for JTAG interface. If DBGSEL is HIGH, this pin is
automatically configured for use with EmbeddedICE (Debug mode).
Input to the RTC oscillator circuit. Input voltage must not exceed 1.8 V.
Output from the RTC oscillator circuit.
Returned test clock output: Extra signal added to the JTAG port. Assists
debugger synchronization when processor frequency varies. Bidirectional pin
with internal pull-up.
Input to the oscillator circuit and internal clock generator circuits. Input voltage
must not exceed 1.8 V.
Output from the oscillator amplifier.
Debug select: When LOW, the part operates normally. When externally
pulled HIGH at reset, P0.27 to P0.31 are configured as JTAG port, and the
part is in Debug mode
External reset input: A LOW on this pin resets the device, causing I/O ports
and peripherals to take on their default states and processor execution to
begin at address 0. TTL with hysteresis, 5 V tolerant.
Rev. 04 — 2 June 2009
[9]
. Input with internal pull-down.
Single-chip 16-bit/32-bit microcontrollers
LPC2101/02/03
© NXP B.V. 2009. All rights reserved.
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