EP9307-CRZ Cirrus Logic Inc, EP9307-CRZ Datasheet - Page 303

• Manufacturer Part Number: EP9307-CRZ
• Description: IC ARM9 SOC ARM920T 272TFBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9307-CRZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 272-TFBGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 14
• Ram Memory Size: 32MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 1
• Digital Ic Case Style: TFBGA
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9307A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1133 - KIT DEVELOPMENT EP9307 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1138

DS785UM1
9.1.1 Detailed Description
9.1.1.1 Host Interface and Descriptor Processor
9.1 Introduction
The Ethernet LAN Controller incorporates all the logic needed to interface directly to the AHB
and to the Media Independent Interface (MII). It includes local memory and DMA control, and
supports full duplex operation with flow control support.
diagram.
This block was designed with a RAM of 544 words, each word containing 33 bits. These
RAMs are used for packet buffering and controller data storage. One RAM is dedicated to the
receiver, and one dedicated to the transmitter. These RAMs are mapped into the register
space and are accessible via the AHB.
The Host Interface can be functionally decomposed into the AHB Interface Controller and the
Descriptor Processor. The AHB Interface Controller implements the actual connection to the
AHB. The controller responds as a AHB bus slave for register programming, and acts as an
AHB bus master for data transfers.
AHB
AHB
Interface
1/10/100 MBPS Ethernet LAN Controller
Figure 9-1. 1/10/100 Mbps Ethernet LAN Controller Block Diagram
TX/RX
Descriptor
Processors
91/10/100 Mbps Ethernet LAN Controller
Copyright 2007 Cirrus Logic
MAC
Reconciliation
Sub-layer
Figure 9-1
MII
shows a simplified block
1/10/100
Mbit
Phy
(External)
Chapter 9
9-1
9