EP9307-CRZ Cirrus Logic Inc, EP9307-CRZ Datasheet - Page 683

• Manufacturer Part Number: EP9307-CRZ
• Description: IC ARM9 SOC ARM920T 272TFBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9307-CRZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 272-TFBGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 14
• Ram Memory Size: 32MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 1
• Digital Ic Case Style: TFBGA
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9307A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1133 - KIT DEVELOPMENT EP9307 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1138

I2SRXClkCfg
DS785UM1
31
15
Address:
Default:
Definition:
Bit Descriptions:
30
14
29
13
28
12
i2s_mstr:
i2s_trel:
i2s_tckp:
i2s_tlrs:
0x8082_0004 - Read/Write
0x0000_0000
Receiver clock configuration register.
RSVD:
RSVD
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Defines if the TX Audio clocks are
slave or master.
0 - slave mode.
1 - master mode.
Determines the timing of the lrckt with respect to the sdox
data outputs.
0 - Transition of lrckt occurs together with the first data bit.
1 - Transition of lrckt occurs one bitclk cycle before the first
sdox data bit. This is I
Defines polarity of the TX bitclk.
1 - Positive clock polarity. The lrckt and sdox lines change
synchronously with the positive edge of the bitclk and are
considered valid during negative transitions.
0 - Negative clock polarity. The lrckt and sdox lines change
synchronously with the negative edge of the bitclk and are
considered valid during positive transitions.
Defines the polarity of lrckt.
0 - if lrckt is low, then it is the left word, if lrckt is high, then
it is the right word.
1 - if lrckt is low, then it is the right word, if lrckt is high,
then it is the left word.
Reserved. Unknown During Read.
24
8
RSVD
23
7
22
6
i2s_rx_bcr
21
5
2
S format.
i2s_rx_nbcg
20
4
i2s_mstr
19
3
EP93xx User’s Guide
i2s_rrel
18
2
I
i2s_rckp
2
S Controller
17
1
i2s_rlrs
21-27
16
0
21