ST72F324LJ2T5 STMicroelectronics, ST72F324LJ2T5 Datasheet - Page 41

IC MCU 8BIT 8K FLASH 44-LQFP

ST72F324LJ2T5

Manufacturer Part Number
ST72F324LJ2T5
Description
IC MCU 8BIT 8K FLASH 44-LQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet

Specifications of ST72F324LJ2T5

Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
32
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-10°C ~ 85°C
Package / Case
44-LQFP
Processor Series
ST72F3x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
384 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
32
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20J-EMU3, STX-RLINK
Minimum Operating Temperature
- 10 C
On-chip Adc
10 bit, 12 Channel
For Use With
497-6421 - BOARD EVAL DGTL BATT CHGR DESIGN497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
497-8242
ST72F324LJ2T5

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ST72F324LJ2T5
Manufacturer:
STMicroelectronics
Quantity:
10 000
Part Number:
ST72F324LJ2T5
Manufacturer:
ST
Quantity:
20 000
Part Number:
ST72F324LJ2T5TR
Manufacturer:
STMicroelectronics
Quantity:
10 000
I/O PORTS (Cont’d)
Figure 26. I/O Port General Block Diagram
Table 11. I/O Port Mode Options
Legend: NI - not implemented
Input
Output
REGISTER
ACCESS
SOURCE (ei
EXTERNAL
INTERRUPT
DDR SEL
Off - implemented not activated
On - implemented and activated
OR SEL
DR SEL
Floating with/without Interrupt
Pull-up with/without Interrupt
Push-pull
Open Drain (logic level)
True Open Drain
DDR
Configuration Mode
x
DR
OR
)
ALTERNATE
OUTPUT
ALTERNATE
ENABLE
If implemented
1
0
1
0
Pull-Up
Off
On
Off
NI
Note: The diode to V
true open drain pads. A local protection between
the pad and V
vice against positive stress.
N-BUFFER
PULL-UP
CONDITION
P-Buffer
Off
On
Off
NI
SS
SCHMITT
TRIGGER
CMOS
is implemented to protect the de-
V
DD
DD
NI (see note)
to V
is not implemented in the
On
P-BUFFER
(see table below)
DD
V
Diodes
DD
DIODES
(see table below)
PULL-UP
(see table below)
ALTERNATE
ST72324Lxx
ANALOG
INPUT
to V
INPUT
PAD
On
SS
41/154
1

Related parts for ST72F324LJ2T5