ST72F324LJ2T5 STMicroelectronics, ST72F324LJ2T5 Datasheet - Page 75

• Manufacturer Part Number: ST72F324LJ2T5
• Description: IC MCU 8BIT 8K FLASH 44-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F324LJ2T5

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -10°C ~ 85°C
• Package / Case: 44-LQFP
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20J-EMU3, STX-RLINK
• Minimum Operating Temperature: - 10 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 497-6421 - BOARD EVAL DGTL BATT CHGR DESIGN497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-8242; ST72F324LJ2T5

SERIAL PERIPHERAL INTERFACE (Cont’d)
10.4.3.2 Slave Select Management
As an alternative to using the SS pin to control the
Slave Select signal, the application can choose to
manage the Slave Select signal by software. This
is configured by the SSM bit in the SPICSR regis-
ter (see
In software management, the external SS pin is
free for other application uses and the internal SS
signal level is driven by writing to the SSI bit in the
SPICSR register.
In Master mode:
Figure 45. Generic SS Timing Diagram
Figure 46. Hardware/Software Slave Select Management
– SS internal must be held high continuously
MOSI/MISO
(if CPHA=0)
(if CPHA=1)
Figure
Master SS
Slave SS
Slave SS
46)
SS external pin
SSI bit
Byte 1
SSM bit
1
0
SS internal
In Slave Mode:
There are two cases depending on the data/clock
timing relationship (see
If CPHA=1 (data latched on 2nd clock edge):
If CPHA=0 (data latched on 1st clock edge):
Byte 2
– SS internal must be held low during the entire
– SS internal must be held low during byte
transmission. This implies that in single slave
applications the SS pin either can be tied to
V
ing the SS function by software (SSM= 1 and
SSI=0 in the in the SPICSR register)
transmission and pulled high between each
byte to allow the slave to write to the shift reg-
ister. If SS is not pulled high, a Write Collision
error will occur when the slave writes to the
shift register (see
SS
, or made free for standard I/O by manag-
Byte 3
Section
Figure
10.4.5.3).
45):
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