ST72F260G1M6 STMicroelectronics, ST72F260G1M6 Datasheet - Page 77

MCU 8BIT 4K FLASH ICP 28SOIC

ST72F260G1M6

Manufacturer Part Number
ST72F260G1M6
Description
MCU 8BIT 4K FLASH ICP 28SOIC
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet

Specifications of ST72F260G1M6

Core Processor
ST7
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Data Converters
A/D 6x10b
Processor Series
ST72F2x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C/SCI/SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
22
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7F264-IND/USB, ST72F34X-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
6-ch x 10-bit
Controller Family/series
ST7
No. Of I/o's
22
Ram Memory Size
256Byte
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
For Use With
497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
497-4840

Available stocks

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Price
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ST72F260G1M6
Manufacturer:
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SERIAL PERIPHERAL INTERFACE (Cont’d)
11.4.3.1 Functional Description
A basic example of interconnections between a
single master and a single slave is illustrated in
Figure
The MOSI pins are connected together and the
MISO pins are connected together. In this way
data is transferred serially between master and
slave (most significant bit first).
The communication is always initiated by the mas-
ter. When the master device transmits data to a
slave device via MOSI pin, the slave device re-
Figure 47. Single Master/ Single Slave Application
47.
MSBit
8-BIT SHIFT REGISTER
GENERATOR
CLOCK
SPI
MASTER
LSBit
SCK
MOSI
SS
MISO
+5V
sponds by sending data to the master device via
the MISO pin. This implies full duplex communica-
tion with both data out and data in synchronized
with the same clock signal (which is provided by
the master device via the SCK pin).
To use a single data line, the MISO and MOSI pins
must be connected at each node ( in this case only
simplex communication is possible).
Four possible data/clock timing relationships may
be chosen (see
must be programmed with the same timing mode.
MISO
MOSI
SCK
SS
ST72260Gx, ST72262Gx, ST72264Gx
Figure
8-BIT SHIFT REGISTER
MSBit
Not used if SS is managed
by software
50) but master and slave
SLAVE
LSBit
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