ST72F260G1M6 STMicroelectronics, ST72F260G1M6 Datasheet - Page 81

• Manufacturer Part Number: ST72F260G1M6
• Description: MCU 8BIT 4K FLASH ICP 28SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F260G1M6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Data Converters: A/D 6x10b
• Processor Series: ST72F2x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7F264-IND/USB, ST72F34X-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6-ch x 10-bit
• Controller Family/series: ST7
• No. Of I/o's: 22
• Ram Memory Size: 256Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• For Use With: 497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-4840

SERIAL PERIPHERAL INTERFACE (Cont’d)
11.4.5 Error Flags
11.4.5.1 Master Mode Fault (MODF)
Master mode fault occurs when the master device
has its SS pin pulled low.
When a Master mode fault occurs:
Clearing the MODF bit is done through a software
sequence:
1. A read access to the SPICSR register while the
2. A write to the SPICR register.
Notes: To avoid any conflicts in an application
with multiple slaves, the SS pin must be pulled
high during the MODF bit clearing sequence. The
SPE and MSTR bits may be restored to their orig-
inal state during or after this clearing sequence.
Hardware does not allow the user to set the SPE
and MSTR bits while the MODF bit is set except in
the MODF bit clearing sequence.
In a slave device, the MODF bit can not be set, but
in a multi master configuration the
slave mode with the MODF bit set.
The MODF bit indicates that there might have
been a multi-master conflict and allows software to
handle this using an interrupt routine and either
perform to a reset or return to an application de-
fault state.
Figure 51. Clearing the WCOL bit (Write Collision Flag) Software Sequence
1st Step
2nd Step
– The MODF bit is set and an SPI interrupt re-
– The SPE bit is reset. This blocks all output
– The MSTR bit is reset, thus forcing the Device
quest is generated if the SPIE bit is set.
from the Device and disables the SPI periph-
eral.
into slave mode.
MODF bit is set.
Clearing sequence after SPIF = 1 (end of a data byte transfer)
Clearing sequence before SPIF = 1 (during a data byte transfer)
1st Step
2nd Step
Read SPICSR
Read SPIDR
RESULT
SPIF =0
WCOL=0
Read SPIDR
Read SPICSR
Device
can be in
RESULT
WCOL=0
11.4.5.2 Overrun Condition (OVR)
An overrun condition occurs, when the master de-
vice has sent a data byte and the slave device has
not cleared the SPIF bit issued from the previously
transmitted byte.
When an Overrun occurs:
– The OVR bit is set and an interrupt request is
In this case, the receiver buffer contains the byte
sent after the SPIF bit was last cleared. A read to
the SPIDR register returns this byte. All other
bytes are lost.
The OVR bit is cleared by reading the SPICSR
register.
11.4.5.3 Write Collision Error (WCOL)
A write collision occurs when the software tries to
write to the SPIDR register while a data transfer is
taking place with an external device. When this
happens, the transfer continues uninterrupted;
and the software write will be unsuccessful.
Write collisions can occur both in master and slave
mode. See also
Management" on page
Note: a "read collision" will never occur since the
received data byte is placed in a buffer in which
access is always synchronous with the CPU oper-
ation.
The WCOL bit in the SPICSR register is set if a
write collision occurs.
No SPI interrupt is generated when the WCOL bit
is set (the WCOL bit is a status flag only).
Clearing the WCOL bit is done through a software
sequence (see
generated if the SPIE bit is set.
ST72260Gx, ST72262Gx, ST72264Gx
Note: Writing to the SPIDR regis-
ter instead of reading it does not
reset the WCOL bit
Figure
Section 11.4.3.2 "Slave Select
51).
78.
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