EZ80F93AZ020SG Zilog, EZ80F93AZ020SG Datasheet - Page 17
EZ80F93AZ020SG
Manufacturer Part Number
EZ80F93AZ020SG
Description
IC ACCLAIM MCU 64KB 100LQFP
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F93AZ020SG
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
24
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
100-LQFP
Processor Series
EZ80F93x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
I2C, IrDA, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
24
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F920200ZCOG
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
269-3874
EZ80F93AZ020SG
EZ80F93AZ020SG
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Table 1. 100-Pin LQFP Pin Identification of the eZ80F92 Device (Continued)
PS015313-0508
Pin No Symbol
33
34
35
36
37
38
39
40
41
42
43
44
V
V
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
V
V
DD
SS
DD
SS
Function
Power Supply
Ground
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Power Supply
Ground
Signal Direction
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Description
Power Supply.
Ground.
The data bus transfers data to and from I/O
and memory devices. The eZ80Acclaim!
drives these lines only during Write cycles
when the CPU is the bus master.
The data bus transfers data to and from I/O
and memory devices. The CPU drives these
lines only during Write cycles when the
CPU is the bus master.
The data bus transfers data to and from I/O
and memory devices. The CPU drives these
lines only during Write cycles when the
CPU is the bus master.
The data bus transfers data to and from I/O
and memory devices. The CPU drives these
lines only during Write cycles when the
CPU is the bus master.
The data bus transfers data to and from I/O
and memory devices. The CPU drives these
lines only during Write cycles when the
CPU is the bus master.
The data bus transfers data to and from I/O
and memory devices. The CPU drives these
lines only during Write cycles when the
CPU is the bus master.
The data bus transfers data to and from I/O
and memory devices. The CPU drives these
lines only during Write cycles when the
CPU is the bus master.
The data bus transfers data to and from I/O
and memory devices. The CPU drives these
lines only during Write cycles when the
CPU is the bus master.
Power Supply.
Ground.
Product Specification
Architectural Overview
®
10
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