Z16F3211FI20SG Zilog, Z16F3211FI20SG Datasheet - Page 202

IC ZNEO MCU FLASH 32K 80QFP

Z16F3211FI20SG

Manufacturer Part Number
Z16F3211FI20SG
Description
IC ZNEO MCU FLASH 32K 80QFP
Manufacturer
Zilog
Series
Encore!® ZNEOr
Datasheet

Specifications of Z16F3211FI20SG

Core Processor
ZNEO
Core Size
16-Bit
Speed
20MHz
Connectivity
EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
60
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
80-BQFP
Processor Series
Z16F3x
Core
Zneo
Data Bus Width
16 bit
Data Ram Size
2 B
Interface Type
ESPI, I2C, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
60
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
Z16F2800100ZCOG
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 12 Channel
For Use With
770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
269-4569

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
Z16F3211FI20SG
Manufacturer:
Zilog
Quantity:
131
Part Number:
Z16F3211FI20SG
Manufacturer:
Zilog
Quantity:
10 000
PS022008-0810
Figure 40. ESPI Configured as an SPI Master in a Single Master and Multiple Slave System
Figure 39. ESPI Configured as an SPI Master in a Single Master and Single Slave System
To Slave #2’s SS Pin
To Slave #1’s SS Pin
To Slave’s SS Pin
configured for the ESPI alternate function on the MOSI, MISO, and SCK pins. The GPIO
for the ESPI SS pin is configured in alternate function mode as well though software uses
any GPIO pin(s) to drive one or more slave select lines. If the ESPI SS signal is not used to
drive a slave select the SSIO bit must still be set to 1 in a single master system.
and
From Slave
Figure 40
From Slaves
To Slave
To Slave
To Slaves
To Slaves
displays the ESPI block configured as an SPI master.
MISO
MOSI
SCK
SS
MISO
MOSI
SCK
GPIO
GPIO
P R E L I M I N A R Y
Bit 0
Bit 0
8-bit Shift Register
8-bit Shift Register
ESPI Master
ESPI Master
Bit 7
Bit 7
Baud Rate
Baud Rate
Generator
Generator
Enhanced Serial Peripheral Interface
Product Specification
ZNEO
Z16F Series
Figure 39
186

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