Z16F3211FI20SG Zilog, Z16F3211FI20SG Datasheet - Page 302

• Manufacturer Part Number: Z16F3211FI20SG
• Description: IC ZNEO MCU FLASH 32K 80QFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F3211FI20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-BQFP
• Processor Series: Z16F3x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 2 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4569

®
ZNEO
Z16F Series
Product Specification
286
10 = Destination address decrements
11 = Reserved
SRCCTL—Source control register
00 = Source address does not change
01 = Source address increments
10 = Source address decrements
11 = Reserved
IEOB—Interrupt on end of buffer
0 = Do not generate an interrupt when the DMA completes this buffer
1 = Generate interrupt at the end of this buffer
TXFR—Transfer to new list address. This bit is used only in linked list mode. 
0 = Increment DMAxLAR by 16 at the end of this buffer.
1 = Load the DMAxLAR with the new List Address value from the descriptor.
EOF—End of frame
0 = This is not a End of Frame buffer
1 = This buffer is the end of the current frame
HALT—Halt after this buffer. This bit is used only in linked list mode.
0 = Next descriptor is loaded.
1 = The DMA will halt at the end of this buffer.
CMDSTAT—Command Status Field
On the first transfer of a buffer this field is placed on the CMDBUS and the CMDVALID
is asserted.
If the
bit is set, the DMA requests a status from the peripheral and places it in this
EOF
field. In linked list mode this field get written back to the descriptor.
The DMA does not use this field it simply passes it on. The definitions of these bits are
specified in each peripheral.
PS022008-0810
P R E L I M I N A R Y
DMA Controller