Z16F3211FI20SG Zilog, Z16F3211FI20SG Datasheet - Page 267

IC ZNEO MCU FLASH 32K 80QFP

Z16F3211FI20SG

Manufacturer Part Number
Z16F3211FI20SG
Description
IC ZNEO MCU FLASH 32K 80QFP
Manufacturer
Zilog
Series
Encore!® ZNEOr
Datasheet

Specifications of Z16F3211FI20SG

Core Processor
ZNEO
Core Size
16-Bit
Speed
20MHz
Connectivity
EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
60
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
80-BQFP
Processor Series
Z16F3x
Core
Zneo
Data Bus Width
16 bit
Data Ram Size
2 B
Interface Type
ESPI, I2C, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
60
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
Z16F2800100ZCOG
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 12 Channel
For Use With
770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
269-4569

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
Z16F3211FI20SG
Manufacturer:
Zilog
Quantity:
131
Part Number:
Z16F3211FI20SG
Manufacturer:
Zilog
Quantity:
10 000
Table 127. ADC Clock Prescale Register (ADCCP)
BITS
FIELD
RESET
R/W
ADDR
PS022008-0810
Bit Position
[7:4]
[3]
DIV16
[2]
DIV8
[1]
DIV4
[0]
DIV2
ADC Clock Prescale Register
7
The ADC Clock Prescale register is used to provide a divided system clock to the ADC.
When this register is programmed with 0H, the system clock is used for the ADC Clock.
Value (H) Description
0H
0
1
0
1
0
1
0
1
6
Reserved—must be 0.
DIV16
Clock is not divided.
System Clock is divided by 16 for ADC Clock.
DIV8
Clock is not divided.
System Clock is divided by 8 for ADC Clock.
DIV4
Clock is not divided.
System Clock is divided by 4 for ADC Clock.
DIV2
Clock is not divided.
System Clock is divided by 2 for ADC Clock.
Reserved
R
0
5
P R E L I M I N A R Y
4
FF-E506H
DIV16
3
0
DIV8
2
0
R/W
Product Specification
ZNEO
DIV4
1
0
Analog Functions
Z16F Series
DIV2
0
0
251

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