Z16F2811AL20SG Zilog, Z16F2811AL20SG Datasheet - Page 240

• Manufacturer Part Number: Z16F2811AL20SG
• Description: IC ZNEO MCU FLASH 128K 100LQFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F2811AL20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Processor Series: Z16F2x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 76
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4533

PS022008-0810
Note:
A summary of I
Master Write Transaction with Data DMA
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The following procedure describes the I
10-bit addressing mode, transmitting data to the bus Master.
If the slave sends a Not Acknowledge prior to the last byte, a Not Acknowledge interrupt
occurs. Software must respond to this interrupt by clearing the DMAIF bit and setting the
STOP bit to end the transaction.
Master Read Transaction with Data DMA
In master read transactions, the Master is responsible for the Acknowledge for each data
byte transferred. The Master software must set the NAK bit after the next to the last data
byte has been received or while the last byte is being received. The DMA supports this by
setting the DMA watermark to 0x01, which results in a DMA interrupt when the next to
the last byte has been received. A DMA interrupt also occurs when the last byte is
received. Otherwise, the sequence is similar to that described above for the Master write
transaction.
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The I
Configure the selected DMA channel for I
The I
Initiate the I
Set the DMAIF bit in the I2CMODE register.
The DMA transfers the data, which is to be transmitted to the slave.
When the DMA interrupt occurs, poll the I2CSTAT register until the TDRE bit = 1.
Set the STOP bit in the I2CCTL register. The STOP bit is polled by software to
Clear the DMAIF bit in the I2CMODE register.
Configure the selected DMA channel for I
DMACTL register for the last buffer to be transferred.
error conditions. A Not Acknowledge interrupt occurs on the last byte transferred.
Master mode transactions. The
section, using the
slave acknowledges.
This ensures that the I
byte written by the DMA.
determine when the transaction is actually completed.
DMACTL register for the last buffer to be transferred. Typically one buffer is defined
with a transfer length of N where N bytes are expected to be read from the slave. The
watermark is set to 1 by writing a 0x01 to DMAxLAR[23:16].
2
2
C interrupt must be enabled in the interrupt controller to alert software of any I
C Master/Slave must be configured as defined in the sections above describing
2
2
C transaction as described in the
C transfer of data using the DMA follows.
ACKV
2
C Master/Slave hardware has commenced transmitting the last
P R E L I M I N A R Y
and
ACK
TXI
bits in the I2CSTATE register to determine if the
2
bit in the I2CCTL register must be cleared.
C Master/Slave Controller operating as a Slave in
2
2
C transmit. The IEOB bit must be set in the
C receive. The
Master Address Only Transactions
IEOB
I
2
C Master/Slave Controller
Product Specification
ZNEO
bit must be set in the
Z16F Series
2
C
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