Z16F2811AL20SG Zilog, Z16F2811AL20SG Datasheet - Page 285

• Manufacturer Part Number: Z16F2811AL20SG
• Description: IC ZNEO MCU FLASH 128K 100LQFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F2811AL20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Processor Series: Z16F2x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 76
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4533

DMA Description
PS022008-0810
DMA Register Description
The DMA is used to off load the processor from doing repetitive tasks. DMA transfers
data from one memory address to another memory address. Since all peripherals are
mapped in memory, the DMA transfers data to or from peripherals.
The DMA transfers data from the source address to the destination address. This requires a
read and/or write cycle that is generated by the DMA controller. Each DMA transfer
requires a minimum of two system clock cycles to execute.
The DMA operates in direct or linked list mode. Direct mode and Linked List mode are
almost the same. In Direct mode the software loads the DMA channel registers directly. In
linked list mode the DMA loads its registers from memory.
Each DMA channel consists of 16-bit control register, a 16-bit transfer length register, a
24-bit destination address register, a 24-bit source address register and a 24-bit list address
register (see
Buffers
A buffer is an allocation of contiguous memory bytes. Buffers are allocated by software to
be used by the DMA. The DMA transfers data to or from buffers. A typical application
would be to send data to serial channels such as I
placed in a buffer by software.
Figure
Figure 56. DMA Channel Registers
56).
P R E L I M I N A R Y
DMA Control (DMACTL)
Transfer Length (TXLN)
Destination Address (DAR)
Source Address (SAR)
List Address (LAR)
2
C, UART, and SPI. The data to be sent is
Product Specification
ZNEO
DMA Controller
Z16F Series
269