C8051F338-GM Silicon Laboratories Inc, C8051F338-GM Datasheet - Page 19

IC MCU 16K FLASH 24QFN

C8051F338-GM

Manufacturer Part Number
C8051F338-GM
Description
IC MCU 16K FLASH 24QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F33xr
Datasheets

Specifications of C8051F338-GM

Program Memory Type
FLASH
Program Memory Size
16KB (16K x 8)
Package / Case
24-QFN
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
21
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
I2C/SMBus/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
21
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F336DK
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1427-5
3. Pin Definitions
CNVSTR
XTAL1
XTAL2
Name
C2CK
VREF
P0.0/
P0.2/
P0.3/
P0.6/
GND
RST/
IDA0
P0.1
C2D
P0.4
P0.5
V
DD
’F336/7
Pin
20
19
18
17
16
15
1
3
2
4
5
Table 3.1. Pin Definitions for the C8051F336/7/8/9
’F338/9
Pin
24
23
22
21
20
4
3
5
6
2
1
D I/O or
D I/O or
D I/O or
D I/O or
A I/O or
D I/O or
D I/O or
D I/O or
A Out
D I/O
D I/O
D I/O
Type
A In
A In
A In
A In
A In
A In
D In
A In
A In
A In
D In
Description
Power Supply Voltage.
Ground.
This ground connection is required. The center pad may
optionally be connected to ground also.
Device Reset. Open-drain output of internal POR or V
monitor. An external source can initiate a system reset by
driving this pin low for at least 10 µs.
Clock signal for the C2 Debug Interface.
Bi-directional data signal for the C2 Debug Interface.
Shared with P2.0 on 20-pin packaging and P2.4 on 24-pin
packaging.
Port 0.0.
External VREF input.
Port 0.1.
IDA0 Output.
Port 0.2.
External Clock Input. This pin is the external oscillator
return for a crystal or resonator.
Port 0.3.
External Clock Output. For an external crystal or resonator,
this pin is the excitation driver. This pin is the external clock
input for CMOS, capacitor, or RC oscillator configurations.
Port 0.4.
Port 0.5.
Port 0.6.
ADC0 External Convert Start or IDA0 Update Source Input.
Rev.1.0
C8051F336/7/8/9
DD
19

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