C8051F500-IQ Silicon Laboratories Inc, C8051F500-IQ Datasheet - Page 254
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C8051F500-IQ
Manufacturer Part Number
C8051F500-IQ
Description
IC 8051 MCU 64K FLASH 48-QFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F50xr
Specifications of C8051F500-IQ
Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
48-QFP
Mfg Application Notes
LIN Bootloader AppNote
Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), CAN, LIN, SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
40
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.25 V
Data Converters
A/D 32x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
C8051F5x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
40
Number Of Timers
4
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F500DK
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 32 Channel
Package
48PQFP
Device Core
8051
Family Name
C8051F50x
Maximum Speed
50 MHz
Operating Supply Voltage
2.5|3.3|5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1530 - ADAPTER PROG TOOLSTICK F500336-1529 - PLATFORM PROG TOOLSTCK F500336-1527 - KIT DEV FOR C8051F50X336-1526 - BOARD PROTOTYPE W/C8051F500
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1510
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F500-IQ
Manufacturer:
SiliconL
Quantity:
300
Company:
Part Number:
C8051F500-IQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F500-IQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
C8051F50x-F51x
25.2. SPI0 Master Mode Operation
A SPI master device initiates all data transfers on a SPI bus. SPI0 is placed in master mode by setting the
Master Enable flag (MSTEN, SPI0CN.6). Writing a byte of data to the SPI0 data register (SPI0DAT) when
in master mode writes to the transmit buffer. If the SPI shift register is empty, the byte in the transmit buffer
is moved to the shift register, and a data transfer begins. The SPI0 master immediately shifts out the data
serially on the MOSI line while providing the serial clock on SCK. The SPIF (SPI0CN.7) flag is set to logic
1 at the end of the transfer. If interrupts are enabled, an interrupt request is generated when the SPIF flag
is set. While the SPI0 master transfers data to a slave on the MOSI line, the addressed SPI slave device
simultaneously transfers the contents of its shift register to the SPI master on the MISO line in a full-duplex
operation. Therefore, the SPIF flag serves as both a transmit-complete and receive-data-ready flag. The
data byte received from the slave is transferred MSB-first into the master's shift register. When a byte is
fully shifted into the register, it is moved to the receive buffer where it can be read by the processor by
reading SPI0DAT.
When configured as a master, SPI0 can operate in one of three different modes: multi-master mode, 3-wire
single-master mode, and 4-wire single-master mode. The default, multi-master mode is active when
NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 1. In this mode, NSS is an input to the device, and
is used to disable the master SPI0 when another master is accessing the bus. When NSS is pulled low in
this mode, MSTEN (SPI0CN.6) and SPIEN (SPI0CN.0) are set to 0 to disable the SPI master device, and
a Mode Fault is generated (MODF, SPI0CN.5 = 1). Mode Fault will generate an interrupt if enabled. SPI0
must be manually re-enabled in software under these circumstances. In multi-master systems, devices will
typically default to being slave devices while they are not acting as the system master device. In multi-mas-
ter mode, slave devices can be addressed individually (if needed) using general-purpose I/O pins.
Figure 25.2 shows a connection diagram between two master devices in multiple-master mode.
3-wire single-master mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 0. In this
mode, NSS is not used, and is not mapped to an external port pin through the crossbar. Any slave devices
that must be addressed in this mode should be selected using general-purpose I/O pins. Figure 25.3
shows a connection diagram between a master device in 3-wire master mode and a slave device.
4-wire single-master mode is active when NSSMD1 (SPI0CN.3) = 1. In this mode, NSS is configured as an
output pin, and can be used as a slave-select signal for a single SPI device. In this mode, the output value
of NSS is controlled (in software) with the bit NSSMD0 (SPI0CN.2). Additional slave devices can be
addressed using general-purpose I/O pins. Figure 25.4 shows a connection diagram for a master device in
4-wire master mode and two slave devices.
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Rev. 1.1