C8051F500-IQ Silicon Laboratories Inc, C8051F500-IQ Datasheet - Page 259
![IC 8051 MCU 64K FLASH 48-QFP](/photos/12/17/121756/c8051f500-iq_sml.jpg)
C8051F500-IQ
Manufacturer Part Number
C8051F500-IQ
Description
IC 8051 MCU 64K FLASH 48-QFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F50xr
Specifications of C8051F500-IQ
Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
48-QFP
Mfg Application Notes
LIN Bootloader AppNote
Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), CAN, LIN, SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
40
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.25 V
Data Converters
A/D 32x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
C8051F5x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
40
Number Of Timers
4
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F500DK
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 32 Channel
Package
48PQFP
Device Core
8051
Family Name
C8051F50x
Maximum Speed
50 MHz
Operating Supply Voltage
2.5|3.3|5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1530 - ADAPTER PROG TOOLSTICK F500336-1529 - PLATFORM PROG TOOLSTCK F500336-1527 - KIT DEV FOR C8051F50X336-1526 - BOARD PROTOTYPE W/C8051F500
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1510
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F500-IQ
Manufacturer:
SiliconL
Quantity:
300
Company:
Part Number:
C8051F500-IQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F500-IQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
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SFR Definition 25.1. SPI0CFG: SPI0 Configuration
SFR Address = 0xA1; SFR Page = 0x00
Note: In slave mode, data on MOSI is sampled in the center of each data bit. In master mode, data on MISO is
Name
Reset
Bit
Type
7
6
5
4
3
2
1
0
Bit
sampled one SYSCLK before the end of each data bit, to provide maximum settling time for the slave device.
See Table 25.1 for timing parameters.
SPIBSY
SLVSEL
MSTEN
RXBMT
CKPHA
CKPOL
SPIBSY
NSSIN
Name
SRMT
R
7
0
MSTEN
SPI Busy.
This bit is set to logic 1 when a SPI transfer is in progress (master or slave mode).
Master Mode Enable.
0: Disable master mode. Operate in slave mode.
1: Enable master mode. Operate as a master.
SPI0 Clock Phase.
0: Data centered on first edge of SCK period.
1: Data centered on second edge of SCK period.
SPI0 Clock Polarity.
0: SCK line low in idle state.
1: SCK line high in idle state.
Slave Selected Flag.
This bit is set to logic 1 whenever the NSS pin is low indicating SPI0 is the selected
slave. It is cleared to logic 0 when NSS is high (slave not selected). This bit does
not indicate the instantaneous value at the NSS pin, but rather a de-glitched ver-
sion of the pin input.
NSS Instantaneous Pin Input.
This bit mimics the instantaneous value that is present on the NSS port pin at the
time that the register is read. This input is not de-glitched.
Shift Register Empty (valid in slave mode only).
This bit will be set to logic 1 when all data has been transferred in/out of the shift
register, and there is no new information available to read from the transmit buffer
or write to the receive buffer. It returns to logic 0 when a data byte is transferred to
the shift register from the transmit buffer or by a transition on SCK. SRMT = 1 when
in Master Mode.
Receive Buffer Empty (valid in slave mode only).
This bit will be set to logic 1 when the receive buffer has been read and contains no
new information. If there is new information available in the receive buffer that has
not been read, this bit will return to logic 0. RXBMT = 1 when in Master Mode.
R/W
6
0
CKPHA
R/W
5
0
CKPOL
R/W
Rev. 1.1
4
0
SLVSEL
Function
R
3
0
*
C8051F50x-F51x
NSSIN
*
R
2
1
SRMT
R
1
1
RXBMT
R
0
1
259
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