MC56F8037VLH Freescale Semiconductor, MC56F8037VLH Datasheet - Page 113

IC DSP 16BIT DUAL 64-LQFP

MC56F8037VLH

Manufacturer Part Number
MC56F8037VLH
Description
IC DSP 16BIT DUAL 64-LQFP
Manufacturer
Freescale Semiconductor
Series
56F8xxxr
Datasheet

Specifications of MC56F8037VLH

Core Processor
56800
Core Size
16-Bit
Speed
32MHz
Connectivity
CAN, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Ram Size
4K x 16
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
64-LQFP
Data Bus Width
16 bit
Processor Series
MC56F80xx
Core
56800E
Numeric And Arithmetic Format
Fixed-Point
Device Million Instructions Per Second
32 MIPs
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
53
Data Ram Size
8 KB
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
MC56F8037EVM
Interface Type
SCI, SPI, I2C
Minimum Operating Temperature
- 40 C
Package
64LQFP
Family Name
56F8xxx
Maximum Speed
32 MHz
On-chip Adc
2(8-chx10-bit)
On-chip Dac
2-chx12-bit
Number Of Timers
5
For Use With
MC56F8037EVM - BOARD EVAL FOR MC56F8037
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Note:
6.3.16.1
This bit field is reserved. Each bit must be set to 0.
6.3.16.2
This field selects the alternate function for GPIOA6.
6.3.16.3
This field selects the alternate function for GPIOA5.
6.3.16.4
This field selects the alternate function for GPIOA4.
6.3.16.5
This bit field is reserved. Each bit must be set to 0.
6.3.17
See
Freescale Semiconductor
Base + $13
Section 6.3.16
RESET
Read
Write
0 = FAULT0 - PWM FAULT0 Input (default)
1 = TA0 - Timer A0
00 = PWM5 - PWM5 (default)
01 = FAULT2 - PWM FAULT2 Input
10 = TA3 - Timer A3
11 = Reserved
00 = PWM4 - PWM4 (default)
01 = FAULT1 - PWM FAULT1 Input
10 = TA2 - Timer A2
11 = Reserved
Figure 6-19 GPIO Peripheral Select Register 0 for GPIOA (SIM_GPSA0)
After reset, all I/O pins are GPIO, except the JTAG pins and the RESET pin.
SIM GPIO Peripheral Select Register 1 for GPIOA (SIM_GPSA1)
Reserved—Bits 15–13
Configure GPIOA6 (GPS_A6)—Bit 12
Configure GPIOA5 (GPS_A5)—Bits 11–10
Configure GPIOA4 (GPS_A4)—Bits 9–8
Reserved—Bits 7–0
15
0
0
for general information about GPIO Peripheral Select Registers.
14
0
0
13
0
0
GPS_A6
12
0
56F8037/56F8027 Data Sheet, Rev. 7
11
0
GPS_A5
10
0
9
0
GPS_A4
8
0
7
0
0
6
0
0
5
0
0
4
0
0
3
0
0
2
0
0
Register Descriptions
1
0
0
0
0
0
113

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