MC56F8037VLH Freescale Semiconductor, MC56F8037VLH Datasheet - Page 160

• Manufacturer Part Number: MC56F8037VLH
• Description: IC DSP 16BIT DUAL 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8037VLH

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Data Bus Width: 16 bit
• Processor Series: MC56F80xx
• Core: 56800E
• Numeric And Arithmetic Format: Fixed-Point
• Device Million Instructions Per Second: 32 MIPs
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 53
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MC56F8037EVM
• Interface Type: SCI, SPI, I2C
• Minimum Operating Temperature: - 40 C
• Package: 64LQFP
• Family Name: 56F8xxx
• Maximum Speed: 32 MHz
• On-chip Adc: 2(8-chx10-bit)
• On-chip Dac: 2-chx12-bit
• Number Of Timers: 5
• For Use With: MC56F8037EVM - BOARD EVAL FOR MC56F8037
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

160
SDA
SCL
1. The master mode I
2. The maximum t
3. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
4. A Fast mode I
5. C
Figure 10-15 Timing Definition for Fast and Standard Mode Devices on the I
Set-up time for STOP
condition
Bus free time between
STOP and START
condition
Pulse width of spikes that
must be suppressed by
the input filter
t
f
acknowledge this address byte, a negative hold time can result, depending on the edge rates of the SDA and SCL lines.
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal.
If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
t
released.
rmax
b
S
= total capacitance of the one bus line in pF
Characteristic
+ t
SU; DAT
t
HD; STA
t
LOW
2
C bus device can be used in a Standard mode I
HD; DAT
= 1000 + 250 = 1250ns (according to the Standard mode I
2
C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
t
r
must be met only if the device does not stretch the LOW period (t
t
HD; DAT
Symbol
t
SU; STO
t
BUF
t
Table 10-18 I
SP
t
SU; DAT
t
HIGH
56F8037/56F8027 Data Sheet, Rev. 7
Minimum
t
f
N/A
4.0
4.7
Standard Mode
2
C Timing (Continued)
t
SU; STA
Maximum
2
C bus system, but the requirement t
N/A
—
—
SR
2
t
HD; STA
C bus specification) before the SCL line is
Minimum
0.6
1.3
0
Fast Mode
LOW
t
SP
t
SU; STO
) of the SCL signal.
Maximum
50
—
—
Freescale Semiconductor
SU; DAT
t
r
P
>= 250ns
2
Unit
t
C Bus
s
s
ns
BUF
S