MC56F8037VLH Freescale Semiconductor, MC56F8037VLH Datasheet - Page 175

• Manufacturer Part Number: MC56F8037VLH
• Description: IC DSP 16BIT DUAL 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8037VLH

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Data Bus Width: 16 bit
• Processor Series: MC56F80xx
• Core: 56800E
• Numeric And Arithmetic Format: Fixed-Point
• Device Million Instructions Per Second: 32 MIPs
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 53
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MC56F8037EVM
• Interface Type: SCI, SPI, I2C
• Minimum Operating Temperature: - 40 C
• Package: 64LQFP
• Family Name: 56F8xxx
• Maximum Speed: 32 MHz
• On-chip Adc: 2(8-chx10-bit)
• On-chip Dac: 2-chx12-bit
• Number Of Timers: 5
• For Use With: MC56F8037EVM - BOARD EVAL FOR MC56F8037
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
Clear Receive Done
Interrupt Register
Clear Activity Interrupt
Register
Clear Stop Detect
Interrupt Register
Clear Start Detect
Interrupt Register
Clear General Call
Interrupt Register
Enable Register
Status Register
Transmit FIFO Level
Register
Receive FIFO Level
Register
Transmit Abort
Source Register
Component
Parameter 1 Register
Component
Parameter 2 Register
Component Version 1
Register
Component Version 2
Register
Component Type 1
Register
Component Type 2
Register
Control Register
Divide-By Register
Status Register
Oscillator Control
Register
Clock Check Register
Protection Register
Clock Divider Register
Configuration
Register
Security High Half
Register
Register Name
CLRRXDONE
TXABRTSRC
CLRSTPDET
COMPARM1
COMPARM2
CLRSTDET
Acronym
COMVER1
COMVER2
COMTYP1
COMTYP2
Table 14-1 Legacy and Revised Acronyms (Continued)
CLRACT
CLKCHK
Peripheral Reference
CLRGC
CLKDIV
RXFLR
OCTRL
TXFLR
DIVBY
SECHI
PROT
CNFG
ENBL
STAT
CTRL
STAT
New
Manual
Acronym
FMSECH
Legacy
FMCLKD
OSCTL
PLLCR
PLLDB
PLLSR
FMCR
On-Clock Chip Synthesis (OCCS) Module
56F8037/56F8027 Data Sheet, Rev. 7
I2C_CLR_STAR_DET
I2C_CLR_STOPDET
I2C_CLR_GENCALL
I2C_CLR_RXDONE
I2C_TX_ABRTSRC
I2C_CLRACTIVITY
I2C_COMPARM1
I2C_COMPARM2
I2C_COMVER1
I2C_COMVER2
I2C_COMTYP1
I2C_COMTYP2
OCCS_OCTRL
OCCS_CLCHK
OCCS_DIVBY
OCCS_PROT
OCCS_CTRL
I2C_ENABLE
OCCS_STAT
FM_CLKDIV
I2C_TXFLR
I2C_RXFLR
Acronym
FM_SECHI
FM_CNFG
I2C_STAT
New
Data Sheet
Acronym
PLLCLCHK
PLLPROT
FMSECH
Legacy
FMCLKD
OSCTL
PLLCR
PLLDB
PLLSR
FMCR
Processor Expert
I2C_CLR_STAR_DET
I2C_CLR_STOPDET
I2C_CLR_GENCALL
I2C_CLR_RXDONE
I2C_TX_ABRTSRC
I2C_CLRACTIVITY
I2C_COMPARM1
I2C_COMPARM2
I2C_COMVER1
I2C_COMVER2
I2C_COMTYP1
I2C_COMTYP2
OCCS_CLCHK
OCCS_PROT
I2C_ENABLE
I2C_TXFLR
I2C_RXFLR
Acronym
I2C_STAT
FMCLKD
FMSECH
OSCTL
PLLCR
PLLDB
PLLSR
FMCR
Electrical Design Considerations
Start
Address
Memory
0xF2AC
0xF2AE
0xF2BA
0xF2BC
0xF2FC
0xF2FD
0xF2B0
0xF2B2
0xF2B4
0xF2B6
0xF2B8
0xF2C0
0xF2FA
0xF2FB
0xF2FE
0xF2FF
0xF130
0xF131
0xF132
0xF135
0xF136
0xF137
0xF400
0xF401
0xF403
End
175