MC908AP32CFBE Freescale Semiconductor, MC908AP32CFBE Datasheet - Page 35

• Manufacturer Part Number: MC908AP32CFBE
• Description: IC MCU 32K FLASH 8MHZ 44QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AP32CFBE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, IRSCI, SCI, SPI
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFP
• Controller Family/series: HC08
• No. Of I/o's: 32
• Ram Memory Size: 2KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08AP
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908AP64E, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor
$003A
$003B
$003C
$003D
$003E
$0033
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$0039
$003F
Addr.
Timer 2 Channel 1 Status and
PLL Control Register (PCTL)
PLL Bandwidth Control Reg-
Control Register (T2SC1)
PLL VCO Range Select
Register Name
PLL Reference Divider
PLL Multiplier Select
PLL Multiplier Select
Timer 2 Channel 1
Timer 2 Channel 1
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Select Register
U = Unaffected
Register High
Register High
Register Low
Register Low
Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 9)
(T2CH1H)
(T2CH1L)
Register
(PBWC)
(PMSH)
(PMRS)
(PMDS)
(PMSL)
ister
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
X = Indeterminate
MC68HC908AP Family Data Sheet, Rev. 4
PLLIE
AUTO
CH1F
Bit 15
MUL7
VRS7
Bit 7
Bit 7
0
0
0
0
0
0
0
0
0
0
CH1IE
LOCK
MUL6
VRS6
PLLF
14
6
0
6
0
0
0
0
1
1
0
0
PLLON
MUL5
VRS5
ACQ
13
5
0
0
5
1
0
0
0
0
0
0
0
Indeterminate after reset
Indeterminate after reset
= Unimplemented
MS1A
MUL4
VRS4
BCS
12
4
0
4
0
0
0
0
0
0
0
0
0
ELS1B
MUL11
MUL3
RDS3
PRE1
VRS3
11
3
0
3
0
0
0
0
0
0
0
ELS1A
MUL10
MUL2
RDS2
PRE0
VRS2
10
R
2
0
2
0
0
0
0
0
0
0
= Reserved
TOV1
VPR1
MUL9
MUL1
VRS1
RDS1
1
0
9
1
0
0
0
0
0
0
0
Monitor ROM
CH1MAX
VPR0
MUL8
MUL0
VRS0
RDS0
Bit 0
Bit 8
Bit 0
R
0
0
0
0
0
0
1
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