M30280FAHP#U5B Renesas Electronics America, M30280FAHP#U5B Datasheet - Page 101

• Manufacturer Part Number: M30280FAHP#U5B
• Description: IC M16C/28 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30280FAHP#U5B

• Core Size: 16-Bit
• Program Memory Size: 96KB (96K x 8)
• Core Processor: M16C/60
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Controller Family/series: M16C
• No. Of I/o's: 71
• Ram Memory Size: 8KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• Digital Ic Case Style: LQFP
• Embedded Interface Type: I2C, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

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Figure 9.10 Interrupts Priority Select Circuit
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6
0
C
2
9
2 /
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B
0
0
8
0
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4
J
7
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0 -
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2
3
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0
, 1
IC/OC interrupt 1, I
0
(
Priority level of each interrupt
M
UART2 transmission, NACK2
2
IC/OC base timer, S
0
1
UART2 reception, ACK2
re-oscillation detection
0
6
Low voltage detection
UART 2 bus collision
UART1 transmission
UART0 transmission
Oscillation stop and
7
Key input interrupt
C
IC/OC interrupt 0
UART1 reception
UART0 reception
A/D conversion
Watchdog timer
Address match
2 /
SI/O4, INT5
SI/O3, INT4
Timer B2
Timer B0
Timer A3
Timer A1
Timer B1
Timer A4
Timer A2
Timer A0
, 8
DMA0
DMA1
INT1
INT3
INT2
INT0
I flag
DBC
IPL
NMI
page 81
M
2
C bus interface
1
6
CL
C
/S
2 /
f o
DA
8
3
) B
8
5
Level 0 (initial value)
Lowest
Priority of peripheral function interrupts
(if priority levels are same)
Highest
Interrupt request level resolution output to clock
generation circuit (Figure 7.1)
accepted
Interrupt
request
9. Interrupts